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[WIP] Implement a VHDL backend #122

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e8f73b6
Copy the verilog backend as vhdl_backend.cc
rlee287 May 21, 2020
0bca471
Replace the copyright header with one styled after the ghdl.cc header
rlee287 May 21, 2020
6bedabe
Initial labelling of functions as needing porting or not, subject to …
rlee287 May 22, 2020
7346b71
Update Makefiles to build the new backend as well
rlee287 May 22, 2020
ac43d36
Write VHDL header imports and adjust the autogenerated header comment
rlee287 May 22, 2020
7b08be4
Remove useless '\n' terminator argument from dump_attributes
rlee287 May 22, 2020
1c8e4cc
Use log_experimental to log the fact that the VHDL backend is experim…
rlee287 May 23, 2020
004a03e
Mark dump_attributes as PORTING REQUIRED again
rlee287 May 23, 2020
698fa75
Implement dump_constant and remove decimal option
rlee287 May 23, 2020
a4e4c1c
Merge branch 'master' into vhdl_backend
rlee287 May 23, 2020
14b618c
Port range identifiers in dump_sigchunk
rlee287 May 23, 2020
cac7e92
Port vector concatenation in dump_sigspec
rlee287 May 24, 2020
a6c0fdd
Remove #if 0 section of dump_wire
rlee287 May 24, 2020
3fe06c7
Port dump_memory function
rlee287 May 24, 2020
4f56439
Port dump_conn
rlee287 May 24, 2020
d128c86
Replace keyword list in `id` with VHDL keywords
rlee287 May 25, 2020
6e1b43d
Port dump_cell_expr_uniop and dump_cell_expr_binop
rlee287 May 25, 2020
826226b
Replace $signed with signed in dump_cell_expr_port
rlee287 May 25, 2020
29c63ab
Merge branch 'master' into vhdl_backend
rlee287 May 28, 2020
9e1f859
Port syntax gen of is_reg_wire
rlee287 May 30, 2020
ee90888
Port dump_reg_init
rlee287 May 31, 2020
5b7c9e6
Label dump_reg_init as needing testing
rlee287 Jun 3, 2020
dad6896
Port range syntax of dump_wire (port dump still need adjusting)
rlee287 Jun 3, 2020
ee5c01c
Initial pass of porting dump_cell_expr
rlee287 Jun 3, 2020
b3e271f
Wrap uniop and binop operators in casts when doing arithmetic operation
rlee287 Jun 3, 2020
38472f6
Adjustments to autogenerated IDs to ensure numbered internal signals …
rlee287 Jun 5, 2020
7103321
Avoid wrapping constants with signed/unsigned conversion functions
rlee287 Jun 5, 2020
81989ce
Set default autoprefix of 'n' and enforce nonempty prefix
rlee287 Jun 5, 2020
6e8b878
Update dump_cell_expr_(uni/bin)op for dump_cell_expr_port changes
rlee287 Jun 5, 2020
a14cf54
Adjust dump_const to use single quote STD_LOGIC for 1-wide constants
rlee287 Jun 5, 2020
9f79c7d
Add warning about 1-length vectors to help string
rlee287 Jun 5, 2020
402c7f9
Initial port of module dumping
rlee287 Jun 5, 2020
46626fd
Port bit selection of cellname
rlee287 Jun 5, 2020
014f000
Write function to get a sensitivity set given SigSpecs
rlee287 Jun 6, 2020
9c31e5b
Address Xiretza's review comment
rlee287 Jun 6, 2020
7de3d2b
Copy over $divfloor and $modfloor updates from Yosys
rlee287 Jun 6, 2020
474302b
Merge branch 'master' into vhdl_backend
rlee287 Jun 6, 2020
af3a5b7
Add get_sensitivity_list signature using initializer_list
rlee287 Jun 8, 2020
c31fc4a
Remove extraneous space before operator in dump_cell_expr_uniop
rlee287 Jun 8, 2020
78cc811
Adjust warnings about signals being 1 wide
rlee287 Jun 8, 2020
83c2768
First pass at porting $pmux
rlee287 Jun 8, 2020
8529d14
Fix $pmux dump to use onehot strings instead of aggregates
rlee287 Jun 8, 2020
d7c10fc
Escape ivar_ id's that are incoming as well
rlee287 Jun 8, 2020
3865d76
Properly port $eq and related
rlee287 Jun 9, 2020
a5e59d0
Fix capitalization of X and Z states in constants
rlee287 Jun 13, 2020
9cff95b
For hex consts, push '0's and include width when needed
rlee287 Jun 13, 2020
ad5bbc7
Adjustments to some UNIOPs
rlee287 Jun 13, 2020
6920990
Remove std::set argument version of get_setnsitivity_set
rlee287 Jun 13, 2020
e30fb17
Print error if dump_wire is called on a port
rlee287 Jun 13, 2020
ff18f66
Remove outdated TODOs and adjust comments
rlee287 Jun 13, 2020
9a76111
Split the reg-finding part of dump_process into different function
rlee287 Jun 13, 2020
e2259fb
Replace YS_OVERRIDE macros with override keyword
rlee287 Jul 28, 2020
6118676
Part 1 of porting new FF changes
rlee287 Aug 2, 2020
157e8b3
Misc comments and tidying up
rlee287 Aug 2, 2020
6738129
Make memory_array_types a regular (sorted) set
rlee287 Aug 5, 2020
1f9b1b6
Ignore dump_wire on port instead of raising error
rlee287 Aug 7, 2020
f2575f2
Minor adjustments to PSL cell generation
rlee287 Aug 7, 2020
6e90b3d
Dump $assert cells as regular VHDL assert
rlee287 Aug 9, 2020
890084e
Apply unary or to $logic_not when required
rlee287 Aug 9, 2020
3f9cd3a
Write get_sensitivity_set that takes std::set
rlee287 Aug 10, 2020
0d23d58
Copy over new dumping code and port clocked FF portions of it
rlee287 Aug 10, 2020
98507ff
When dumping a PSL cover statement, use a Sequence (Braced-SERE)
rlee287 Aug 11, 2020
a319f1a
Port latch generation code as well
rlee287 Aug 14, 2020
ef2aea4
Remove obsolete commented-out code for dumping FFs
rlee287 Aug 14, 2020
793e1ab
Merge branch 'master' into vhdl_backend
rlee287 Sep 7, 2020
f6a24ef
Remove defparam option
rlee287 Sep 26, 2020
f844b44
Copy a change from the Verilog backend
rlee287 Sep 26, 2020
cf1341f
Create std08 command line option
rlee287 Oct 9, 2020
1e2dd13
VHDL-93 compliant hex constants when -std08 not specified
rlee287 Oct 9, 2020
1cd293d
More updates on dumping FFs
rlee287 Oct 9, 2020
e014176
More UNIOP handling
rlee287 Oct 9, 2020
95e3d1d
Remove spacing between chunk name and chunk range
rlee287 Oct 13, 2020
3b039c3
Replace "unclocked assertions" warning with "unclocked directives"
rlee287 Oct 13, 2020
506cc97
Rename dump_memory to dump_memory_types
rlee287 Nov 2, 2020
2f9d312
Merge branch 'master' into vhdl_backend
rlee287 Dec 16, 2020
61f9b1f
Include GHDL plugin version in generated VHDL output
rlee287 Dec 16, 2020
626a4c0
Improve handling of $assert and friends
rlee287 Dec 17, 2020
cac3f48
Update various comments in VHDL backend code
rlee287 Dec 17, 2020
613f282
Adjust emitting of ?= and write explanatory comments
rlee287 Dec 17, 2020
14e9562
Port over Mem helper changes from Verilog backend
rlee287 Dec 17, 2020
ea00e7b
Port simple_lhs change from Verilog backend
rlee287 Dec 17, 2020
c25d2ab
Replace -simple-lhs with -nosimple-lhs and only allow this in VHDL-20…
rlee287 Dec 20, 2020
b7967d4
Put parentheses around output of dump_cell_expr_port in case concaten…
rlee287 Dec 20, 2020
fcc110f
Fix lingering assignment = in post-synth cell expr dumping
rlee287 Dec 20, 2020
4070425
Propagate LHS concatenation mode to various cell_expr dumps
rlee287 Dec 20, 2020
94fec4e
Fix mult18x18d component to match yosys verilog
JulianKemmerer Dec 19, 2020
d7a9032
Fix a series of bugs in FF dumping code
rlee287 Dec 21, 2020
ff3be34
Write a process_sensitivity_str helper and use it for process sensiti…
rlee287 Dec 21, 2020
e13584c
Merge branch 'master' into vhdl_backend
rlee287 Jan 1, 2021
6111230
Merge branch 'master' into vhdl_backend
rlee287 Jan 25, 2021
0c6ea58
Slight adjustments to formal cell dumping
rlee287 Feb 11, 2021
f1b5e3c
Mark dump_memory_types as porting complete
rlee287 Feb 11, 2021
ad14b39
Initial (believed working) port of $lut cell dumping
rlee287 Feb 11, 2021
52d1a02
Log warning when emitting VHDL-2008 LHS aggregates
rlee287 Feb 12, 2021
38763f2
Fix more FF bugs by rewriting synchronous signal portion
rlee287 Feb 12, 2021
e6b31e2
Avoid requiring VERSION macro and print "unknown version" if macro is…
rlee287 Feb 12, 2021
32251b2
Update some comments, including an archive source for a (now dead) link
rlee287 Mar 3, 2021
e60aa70
Merge branch 'master' into vhdl_backend
rlee287 Mar 13, 2021
1bd4855
Merge branch 'master' into vhdl_backend
rlee287 Mar 18, 2021
5b24da4
Merge branch 'master' into vhdl_backend
rlee287 Mar 29, 2021
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13 changes: 9 additions & 4 deletions Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -2,6 +2,8 @@

# Name or path to the ghdl executable.
GHDL=ghdl
GIT_VERSION_RAW := "$(shell git describe --dirty --always --tags)"
GIT_VERSION = '$(GIT_VERSION_RAW)'

YOSYS_CONFIG=yosys-config
SOEXT=so
Expand All @@ -14,18 +16,21 @@ LIBGHDL_INC:=$(shell $(GHDL) --libghdl-include-dir)

ALL_LDFLAGS=$(LIBGHDL_LIB) -Wl,-rpath,$(dir $(LIBGHDL_LIB)) $(LDFLAGS)

ALL_CFLAGS=-fPIC -DYOSYS_ENABLE_GHDL -I$(LIBGHDL_INC) $(CFLAGS)
ALL_CFLAGS=-fPIC -DYOSYS_ENABLE_GHDL -DVERSION=$(GIT_VERSION) -I$(LIBGHDL_INC) $(CFLAGS)

all: ghdl.$(SOEXT)

ghdl.$(SOEXT): ghdl.o
$(YOSYS_CONFIG) --build $@ $< -shared $(ALL_LDFLAGS)
ghdl.$(SOEXT): ghdl.o vhdl_backend.o
$(YOSYS_CONFIG) --build $@ $^ -shared $(ALL_LDFLAGS)

ghdl.o: src/ghdl.cc
$(YOSYS_CONFIG) --exec --cxx -c --cxxflags -o $@ $< $(ALL_CFLAGS)

vhdl_backend.o: src/vhdl_backend.cc
$(YOSYS_CONFIG) --exec --cxx -c --cxxflags -o $@ $< $(ALL_CFLAGS)

clean: force
$(RM) -f ghdl.$(SOEXT) ghdl.o
$(RM) -f ghdl.$(SOEXT) ghdl.o vhdl_backend.o

install: ghdl.$(SOEXT)
$(YOSYS_CONFIG) --exec mkdir -p --datdir/plugins
Expand Down
1 change: 1 addition & 0 deletions src/Makefile.inc
Original file line number Diff line number Diff line change
@@ -1,2 +1,3 @@

OBJS += frontends/ghdl/ghdl.o
OBJS += backends/vhdl/vhdl_backend.o
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