Suggested Fix for efabless/caravel#55

Remove the compiler directives related to default port type
heavySea · May 5, 2021 · fdb7d86 · fdb7d86
1 parent 56ec9e6
commit fdb7d86
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diff --git a/verilog/dv/caravel/mgmt_soc/caravan/caravan_tb.v b/verilog/dv/caravel/mgmt_soc/caravan/caravan_tb.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
  *
@@ -211,4 +210,3 @@ module caravan_tb;
 	);
 
 endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v b/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
  *
@@ -193,4 +192,3 @@ module gpio_tb;
 	);
 
 endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v b/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 /*	
 	StriVe housekeeping SPI testbench.
 */
@@ -428,4 +427,3 @@ module hkspi_tb;
 	);
 
 endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v b/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
  *
@@ -200,4 +199,3 @@ module mem_tb;
 	);
 
 endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 `timescale 1 ns / 1 ps
 
@@ -173,4 +172,3 @@ module mprj_ctrl_tb;
 	);
 
 endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v b/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 /*	
  *	StriVe housekeeping pass-thru mode SPI testbench.
  */
@@ -347,4 +346,3 @@ module pass_thru_tb;
 	);
 
 endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v b/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
  *
@@ -156,4 +155,3 @@ module perf_tb;
 	);
 
 endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v b/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 `timescale 1 ns / 1 ps
 
@@ -155,4 +154,3 @@ module pll_tb;
 	);
 
 endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/qspi/qspi_tb.v b/verilog/dv/caravel/mgmt_soc/qspi/qspi_tb.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
  *
@@ -202,4 +201,3 @@ module qspi_tb;
 	);
 
 endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v b/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
  *
@@ -187,4 +186,3 @@ module storage_tb;
 	);
 
 endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v b/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 `timescale 1 ns / 1 ps
 
@@ -217,4 +216,3 @@ module sysctrl_tb;
 	);
 
 endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v b/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
  *
@@ -198,4 +197,3 @@ module timer_tb;
 	);
 
 endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v b/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
  *
@@ -226,4 +225,3 @@ module timer2_tb;
 	);
 
 endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v b/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
  *
@@ -147,4 +146,3 @@ module uart_tb;
 	);
 
 endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/spiflash.v b/verilog/dv/caravel/spiflash.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017 Clifford Wolf
  *

diff --git a/verilog/dv/caravel/tbuart.v b/verilog/dv/caravel/tbuart.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017 Clifford Wolf
  *

diff --git a/verilog/dv/dummy_slave.v b/verilog/dv/dummy_slave.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 module dummy_slave(
     input wb_clk_i,
     input wb_rst_i,

diff --git a/verilog/dv/wb_utests/chip_io/chip_io_tb.v b/verilog/dv/wb_utests/chip_io/chip_io_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 `timescale 1 ns / 1 ps
 

diff --git a/verilog/dv/wb_utests/gpio_wb/gpio_wb_tb.v b/verilog/dv/wb_utests/gpio_wb/gpio_wb_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 
 `timescale 1 ns / 1 ps

diff --git a/verilog/dv/wb_utests/intercon_wb/intercon_wb_tb.v b/verilog/dv/wb_utests/intercon_wb/intercon_wb_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 
 `timescale 1 ns / 1 ps

diff --git a/verilog/dv/wb_utests/la_wb/la_wb_tb.v b/verilog/dv/wb_utests/la_wb/la_wb_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 `timescale 1 ns / 1 ps
 
 `include "la_wb.v"

diff --git a/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v b/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 
 `timescale 1 ns / 1 ps

diff --git a/verilog/dv/wb_utests/mgmt_protect/mgmt_protect_tb.v b/verilog/dv/wb_utests/mgmt_protect/mgmt_protect_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 
 `timescale 1 ns / 1 ps

diff --git a/verilog/dv/wb_utests/mprj_ctrl/mprj_ctrl_tb.v b/verilog/dv/wb_utests/mprj_ctrl/mprj_ctrl_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 
 `timescale 1 ns / 1 ps

diff --git a/verilog/dv/wb_utests/spi_sysctrl_wb/spi_sysctrl_wb_tb.v b/verilog/dv/wb_utests/spi_sysctrl_wb/spi_sysctrl_wb_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 
 `timescale 1 ns / 1 ps

diff --git a/verilog/dv/wb_utests/spimemio_wb/spimemio_wb_tb.v b/verilog/dv/wb_utests/spimemio_wb/spimemio_wb_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 
 `timescale 1 ns / 1 ps

diff --git a/verilog/dv/wb_utests/storage_wb/storage_wb_tb.v b/verilog/dv/wb_utests/storage_wb/storage_wb_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 // `define DBG
 
 `define STORAGE_BASE_ADR  32'h0100_0000

diff --git a/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v b/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 `timescale 1 ns / 1 ps
 

diff --git a/verilog/dv/wb_utests/uart_wb/uart_wb_tb.v b/verilog/dv/wb_utests/uart_wb/uart_wb_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 
 `timescale 1 ns / 1 ps

diff --git a/verilog/gl/__user_project_wrapper.v b/verilog/gl/__user_project_wrapper.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 /*
  *-------------------------------------------------------------
  *

diff --git a/verilog/gl/gpio_control_block.v b/verilog/gl/gpio_control_block.v
@@ -1,4 +1,3 @@
-`default_nettype wire
 module gpio_control_block (mgmt_gpio_in,
     mgmt_gpio_oeb,
     mgmt_gpio_out,

diff --git a/verilog/gl/storage.v b/verilog/gl/storage.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 /* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
 
 module storage(mgmt_clk, mgmt_ena_ro, VPWR, VGND, mgmt_addr, mgmt_addr_ro, mgmt_ena, mgmt_rdata, mgmt_rdata_ro, mgmt_wdata, mgmt_wen, mgmt_wen_mask);

diff --git a/verilog/rtl/DFFRAM.v b/verilog/rtl/DFFRAM.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 `ifndef USE_CUSTOM_DFFRAM
 
 module DFFRAM(

diff --git a/verilog/rtl/DFFRAMBB.v b/verilog/rtl/DFFRAMBB.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 /*
     Building blocks for DFF based RAM compiler for SKY130A 
     BYTE        :   8 memory cells used as a building block for WORD module

diff --git a/verilog/rtl/__user_analog_project_wrapper.v b/verilog/rtl/__user_analog_project_wrapper.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 /*
  *-------------------------------------------------------------
  *

diff --git a/verilog/rtl/__user_project_wrapper.v b/verilog/rtl/__user_project_wrapper.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 /*
  *-------------------------------------------------------------
  *

diff --git a/verilog/rtl/caravan.v b/verilog/rtl/caravan.v
@@ -1,4 +1,3 @@
-// `default_nettype none
 // SPDX-FileCopyrightText: 2020 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
@@ -864,4 +863,3 @@ module caravan (
 	);
 
 endmodule
-// `default_nettype wire
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
@@ -1,4 +1,3 @@
-// `default_nettype none
 // SPDX-FileCopyrightText: 2020 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
@@ -801,4 +800,3 @@ module caravel (
 	);
 
 endmodule
-// `default_nettype wire
diff --git a/verilog/rtl/caravel_clocking.v b/verilog/rtl/caravel_clocking.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 // This routine synchronizes the 
 
 module caravel_clocking(
@@ -108,4 +107,3 @@ module caravel_clocking(
     assign resetb_sync = ~(reset_delay[0] | ext_reset);
 
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/chip_io.v b/verilog/rtl/chip_io.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-// `default_nettype none
 module chip_io(
 	// Package Pins
 	inout  vddio,		// Common padframe/ESD supply
@@ -362,4 +361,3 @@ module chip_io(
 	);
 
 endmodule
-// `default_nettype wire
diff --git a/verilog/rtl/chip_io_alt.v b/verilog/rtl/chip_io_alt.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-// `default_nettype none
 
 /* Alternative padframe that removes the GPIO from the top row,	*/
 /* replacing them with un-overlaid power pads which have a	*/
@@ -446,4 +445,3 @@ module chip_io_alt #(
 	);
 
 endmodule
-// `default_nettype wire
diff --git a/verilog/rtl/clock_div.v b/verilog/rtl/clock_div.v
@@ -14,7 +14,6 @@
 // SPDX-License-Identifier: Apache-2.0
 
 /* Integer-N clock divider */
-`default_nettype none
 
 module clock_div #(
     parameter SIZE = 3		// Number of bits for the divider value
@@ -210,4 +209,3 @@ module even #(
     end
 
 endmodule //even
-`default_nettype wire