Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

CI workflow for SystemVerilog syntax checking #46

Merged
merged 17 commits into from
Aug 14, 2024
Merged

Conversation

Muxianesty
Copy link
Collaborator

This Pull Request introduces a new CI workflow, which uses Verilator to check generated SystemVerilog for syntax errors. Additionally, example configurations were expanded and renamed to match the ones used in tests.

@Muxianesty Muxianesty added enhancement New feature or request stage II For issues applicable to Stage II of the project labels Aug 8, 2024
@Muxianesty Muxianesty requested a review from ssmolov August 8, 2024 16:30
@Muxianesty Muxianesty self-assigned this Aug 8, 2024
@@ -0,0 +1,95 @@
name: check-verilog
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Why check-verilog name is used, if SystemVerilog description is tested?

Copy link
Collaborator Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Fixed.

Comment on lines 19 to 20
MODULE_OUTPUT_PATH: "output.sv"
LIBRARY_OUTPUT_PATH: "lib.sv"
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

These environment variables are used at specific jobs/steps only. It would be better to declare them locally (well, as-local-as-possible).

Copy link
Collaborator Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Fixed.

LIBRARY_OUTPUT_PATH: "lib.sv"

jobs:
build-and-parse-verilog:
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

First of all, not "verilog" but "systemverilog", or, probably, "sv".

Also this job name looks a bit straightforward. What if one more step, (for example, logic synthesis) will be added here? What name will be used -- "build-and-parse-and-synthesize-systemverilog"? I'd use more general name like "synth-sv" -- our main task is to perform good HLS, and we can omit extra details here and write a describing comment, if needed,

Copy link
Collaborator Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Fixed.

.github/workflows/check_verilog.yml Outdated Show resolved Hide resolved
strategy:
matrix:
kernel: [polynomial2, scalar3, matrixmul2, muxmul, addconst, movingsum]
config: [1]
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

What does it mean? Numbers aren't illustrative, by the way.

Copy link
Collaborator Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Fixed with different configuration naming.

build-and-parse-verilog:
strategy:
matrix:
kernel: [polynomial2, scalar3, matrixmul2, muxmul, addconst, movingsum]
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Probably a lexicographical order would be more deterministic for future kernels adding

Copy link
Collaborator Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Fixed.

README.md Outdated
@@ -276,7 +276,7 @@ For example, given subdirectory `polynomial2`, the compilation and execution com
```bash
cmake -S . -B build -G Ninja -DCMAKE_PREFIX_PATH=~/firtool-1.72.0 -DSRC_FILES="~/utopia-hls/examples/polynomial2/polynomial2.cpp"
cmake --build build
build/src/umain hls --config examples/polynomial2/polynomial2.json -a --out-sv output
build/src/umain hls --config examples/polynomial2/polynomial2_1.json -a --out-sv output
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

What are these "_1" and "_2" filename suffixes for? Looks ugly.

Copy link
Collaborator Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Fixed.

matrix:
kernel: [addconst, matrixmul2, movingsum, muxmul, polynomial2, scalar3]
config: [STUB]
## A workaround to intiailize an empty config array.
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

intiailize -> initialize

Copy link
Collaborator Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Fixed.

Comment on lines 37 to 40
- kernel: movingsum
config: add_int_2
- kernel: movingsum
config: add_int_8
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Is it a good practice to enumerate different configs for same kernel in such way? Can't we do something like:

- kernel: somekernel
  config: [config1, config2]

?

Copy link
Collaborator Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Already tried it 1-2 commits before. Instead of what we want Github parses it as a JSON array of two elements.

@ssmolov ssmolov merged commit abb1719 into master Aug 14, 2024
10 checks passed
@Muxianesty Muxianesty deleted the check_verilog_ci branch August 15, 2024 14:20
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
enhancement New feature or request stage II For issues applicable to Stage II of the project
Projects
None yet
Development

Successfully merging this pull request may close these issues.

2 participants