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[RISCV] Add vcpop.m/vfirst.m to RISCVMaskedPseudosTable #115162

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merged 4 commits into from
Nov 7, 2024
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[RISCV] Add vcpop.m/vfirst.m to RISCVMaskedPseudosTable #115162

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d66d8b6
[𝘀𝗽𝗿] changes to main this commit is based on
wangpc-pp Nov 6, 2024
7e72631
[𝘀𝗽𝗿] initial version
wangpc-pp Nov 6, 2024
224be13
[𝘀𝗽𝗿] changes introduced through rebase
wangpc-pp Nov 7, 2024
1478ea7
Move to near def
wangpc-pp Nov 7, 2024
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14 changes: 12 additions & 2 deletions llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3708,6 +3708,15 @@ static bool isImplicitDef(SDValue V) {
return V.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF;
}

static bool hasGPROut(unsigned Opc) {
switch (RISCV::getRVVMCOpcode(Opc)) {
case RISCV::VCPOP_M:
case RISCV::VFIRST_M:
return true;
}
return false;
}

// Optimize masked RVV pseudo instructions with a known all-ones mask to their
// corresponding "unmasked" pseudo versions. The mask we're interested in will
// take the form of a V0 physical register operand, with a glued
Expand Down Expand Up @@ -3737,8 +3746,9 @@ bool RISCVDAGToDAGISel::doPeepholeMaskedRVV(MachineSDNode *N) {
#endif

SmallVector<SDValue, 8> Ops;
// Skip the passthru operand at index 0 if !UseTUPseudo.
for (unsigned I = !UseTUPseudo, E = N->getNumOperands(); I != E; I++) {
// Skip the passthru operand at index 0 if !UseTUPseudo and no GPR out.
bool ShouldSkip = !UseTUPseudo && !hasGPROut(Opc);
for (unsigned I = ShouldSkip, E = N->getNumOperands(); I != E; I++) {
// Skip the mask, and the Glue.
SDValue Op = N->getOperand(I);
if (I == MaskOpIdx || Op.getValueType() == MVT::Glue)
Expand Down
2 changes: 2 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
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Expand Up @@ -1983,6 +1983,7 @@ multiclass VPseudoVPOP_M {
def "_M_" # mti.BX : VPseudoUnaryNoMaskGPROut,
SchedBinary<"WriteVMPopV", "ReadVMPopV", "ReadVMPopV", mx>;
def "_M_" # mti.BX # "_MASK" : VPseudoUnaryMaskGPROut,
RISCVMaskedPseudo<MaskIdx=1>,
SchedBinary<"WriteVMPopV", "ReadVMPopV", "ReadVMPopV", mx>;
}
}
Expand All @@ -1995,6 +1996,7 @@ multiclass VPseudoV1ST_M {
def "_M_" #mti.BX : VPseudoUnaryNoMaskGPROut,
SchedBinary<"WriteVMFFSV", "ReadVMFFSV", "ReadVMFFSV", mx>;
def "_M_" # mti.BX # "_MASK" : VPseudoUnaryMaskGPROut,
RISCVMaskedPseudo<MaskIdx=1>,
SchedBinary<"WriteVMFFSV", "ReadVMFFSV", "ReadVMFFSV", mx>;
}
}
Expand Down
10 changes: 2 additions & 8 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
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Expand Up @@ -1797,11 +1797,8 @@ define float @vreduce_fminimum_v7f32(ptr %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmset.m v0
; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma
; CHECK-NEXT: vmfne.vv v10, v8, v8
; CHECK-NEXT: vcpop.m a0, v10, v0.t
; CHECK-NEXT: vcpop.m a0, v10
; CHECK-NEXT: beqz a0, .LBB111_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: lui a0, 523264
Expand Down Expand Up @@ -2558,11 +2555,8 @@ define float @vreduce_fmaximum_v7f32(ptr %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmset.m v0
; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma
; CHECK-NEXT: vmfne.vv v10, v8, v8
; CHECK-NEXT: vcpop.m a0, v10, v0.t
; CHECK-NEXT: vcpop.m a0, v10
; CHECK-NEXT: beqz a0, .LBB139_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: lui a0, 523264
Expand Down
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