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[FMV][AArch64] Simplify version selection according to ACLE. #121921

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Merged
merged 7 commits into from
Jan 8, 2025
Merged

[FMV][AArch64] Simplify version selection according to ACLE. #121921

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785c6ec
[FMV][AArch64] Simplify version selection according to ACLE.
labrinea Jan 7, 2025
24e9178
Use bitmask for FMV priority and add a corresponding test.
labrinea Jan 7, 2025
9391d8d
Merge branch 'main' into fmv-priority
labrinea Jan 7, 2025
89b8c63
Move FeatPriorities in a separate file because AArch64CPUFeatures.inc
labrinea Jan 8, 2025
f197b26
Forgot to add the new file AArch64FeatPriorities.inc
labrinea Jan 8, 2025
665b4f1
reference ACLE pull request on test file
labrinea Jan 8, 2025
1d9d131
Merge branch 'main' into fmv-priority
labrinea Jan 8, 2025
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2 changes: 1 addition & 1 deletion clang/include/clang/Basic/TargetInfo.h
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Expand Up @@ -1531,7 +1531,7 @@ class TargetInfo : public TransferrableTargetInfo,

// Return the target-specific priority for features/cpus/vendors so
// that they can be properly sorted for checking.
virtual unsigned getFMVPriority(ArrayRef<StringRef> Features) const {
virtual uint64_t getFMVPriority(ArrayRef<StringRef> Features) const {
return 0;
}

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2 changes: 1 addition & 1 deletion clang/lib/Basic/Targets/AArch64.cpp
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Expand Up @@ -714,7 +714,7 @@ AArch64TargetInfo::getVScaleRange(const LangOptions &LangOpts) const {
return std::nullopt;
}

unsigned AArch64TargetInfo::getFMVPriority(ArrayRef<StringRef> Features) const {
uint64_t AArch64TargetInfo::getFMVPriority(ArrayRef<StringRef> Features) const {
return llvm::AArch64::getFMVPriority(Features);
}

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2 changes: 1 addition & 1 deletion clang/lib/Basic/Targets/AArch64.h
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Expand Up @@ -137,7 +137,7 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public TargetInfo {
void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
bool setCPU(const std::string &Name) override;

unsigned getFMVPriority(ArrayRef<StringRef> Features) const override;
uint64_t getFMVPriority(ArrayRef<StringRef> Features) const override;

bool useFP16ConversionIntrinsics() const override {
return false;
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4 changes: 2 additions & 2 deletions clang/lib/Basic/Targets/RISCV.cpp
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Expand Up @@ -489,7 +489,7 @@ ParsedTargetAttr RISCVTargetInfo::parseTargetAttr(StringRef Features) const {
return Ret;
}

unsigned RISCVTargetInfo::getFMVPriority(ArrayRef<StringRef> Features) const {
uint64_t RISCVTargetInfo::getFMVPriority(ArrayRef<StringRef> Features) const {
// Priority is explicitly specified on RISC-V unlike on other targets, where
// it is derived by all the features of a specific version. Therefore if a
// feature contains the priority string, then return it immediately.
Expand All @@ -501,7 +501,7 @@ unsigned RISCVTargetInfo::getFMVPriority(ArrayRef<StringRef> Features) const {
Feature = RHS;
else
continue;
unsigned Priority;
uint64_t Priority;
if (!Feature.getAsInteger(0, Priority))
return Priority;
}
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2 changes: 1 addition & 1 deletion clang/lib/Basic/Targets/RISCV.h
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Expand Up @@ -122,7 +122,7 @@ class RISCVTargetInfo : public TargetInfo {
void fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const override;
bool supportsTargetAttributeTune() const override { return true; }
ParsedTargetAttr parseTargetAttr(StringRef Str) const override;
unsigned getFMVPriority(ArrayRef<StringRef> Features) const override;
uint64_t getFMVPriority(ArrayRef<StringRef> Features) const override;

std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override {
return std::make_pair(32, 32);
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6 changes: 3 additions & 3 deletions clang/lib/Basic/Targets/X86.cpp
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Expand Up @@ -1357,8 +1357,8 @@ static llvm::X86::ProcessorFeatures getFeature(StringRef Name) {
// correct, so it asserts if the value is out of range.
}

unsigned X86TargetInfo::getFMVPriority(ArrayRef<StringRef> Features) const {
auto getPriority = [](StringRef Feature) -> unsigned {
uint64_t X86TargetInfo::getFMVPriority(ArrayRef<StringRef> Features) const {
auto getPriority = [](StringRef Feature) -> uint64_t {
// Valid CPUs have a 'key feature' that compares just better than its key
// feature.
using namespace llvm::X86;
Expand All @@ -1372,7 +1372,7 @@ unsigned X86TargetInfo::getFMVPriority(ArrayRef<StringRef> Features) const {
return getFeaturePriority(getFeature(Feature)) << 1;
};

unsigned Priority = 0;
uint64_t Priority = 0;
for (StringRef Feature : Features)
if (!Feature.empty())
Priority = std::max(Priority, getPriority(Feature));
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2 changes: 1 addition & 1 deletion clang/lib/Basic/Targets/X86.h
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Expand Up @@ -384,7 +384,7 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo {
return CPU != llvm::X86::CK_None;
}

unsigned getFMVPriority(ArrayRef<StringRef> Features) const override;
uint64_t getFMVPriority(ArrayRef<StringRef> Features) const override;

bool setFPMath(StringRef Name) override;

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2 changes: 1 addition & 1 deletion clang/lib/CodeGen/CodeGenModule.cpp
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Expand Up @@ -4241,7 +4241,7 @@ void CodeGenModule::EmitGlobalDefinition(GlobalDecl GD, llvm::GlobalValue *GV) {
static void ReplaceUsesOfNonProtoTypeWithRealFunction(llvm::GlobalValue *Old,
llvm::Function *NewFn);

static unsigned getFMVPriority(const TargetInfo &TI,
static uint64_t getFMVPriority(const TargetInfo &TI,
const CodeGenFunction::FMVResolverOption &RO) {
llvm::SmallVector<StringRef, 8> Features{RO.Features};
if (RO.Architecture)
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55 changes: 55 additions & 0 deletions clang/test/CodeGen/AArch64/fmv-priority.c
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@@ -0,0 +1,55 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --include-generated-funcs --version 5
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -emit-llvm -o - %s | FileCheck %s

// Priority biskmasks after feature dependency expansion:
//
// MSB LSB
//
// sme2 | ls64 | sme | bf16 | | | fp16 | simd | fp
// -----+------+-----+------+-------+------+------+------+---
// sme2 | | sme | bf16 | rcpc2 | rcpc | fp16 | simd | fp
//
// Dependencies should not affect priorities, since a
// feature can only depend on lower priority features:
// https://github.com/ARM-software/acle/pull/376

__attribute__((target_version("sme2+ls64"))) int fn(void);
__attribute__((target_version("sme2+rcpc2"))) int fn(void);
__attribute__((target_version("default"))) int fn(void) { return 0; }

int call() { return fn(); }

// CHECK-LABEL: define dso_local i32 @fn.default(
// CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: ret i32 0
//
//
// CHECK-LABEL: define dso_local i32 @call(
// CHECK-SAME: ) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[CALL:%.*]] = call i32 @fn()
// CHECK-NEXT: ret i32 [[CALL]]
//
//
// CHECK-LABEL: define weak_odr ptr @fn.resolver() comdat {
// CHECK-NEXT: [[RESOLVER_ENTRY:.*:]]
// CHECK-NEXT: call void @__init_cpu_features_resolver()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 153126785511392000
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 153126785511392000
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
// CHECK-NEXT: br i1 [[TMP3]], label %[[RESOLVER_RETURN:.*]], label %[[RESOLVER_ELSE:.*]]
// CHECK: [[RESOLVER_RETURN]]:
// CHECK-NEXT: ret ptr @fn._Mls64Msme2
// CHECK: [[RESOLVER_ELSE]]:
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 144119586269233920
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 144119586269233920
// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
// CHECK-NEXT: br i1 [[TMP7]], label %[[RESOLVER_RETURN1:.*]], label %[[RESOLVER_ELSE2:.*]]
// CHECK: [[RESOLVER_RETURN1]]:
// CHECK-NEXT: ret ptr @fn._Mrcpc2Msme2
// CHECK: [[RESOLVER_ELSE2]]:
// CHECK-NEXT: ret ptr @fn.default
//
48 changes: 24 additions & 24 deletions clang/test/CodeGen/attr-target-clones-aarch64.c
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Expand Up @@ -64,20 +64,20 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_cpu_features_resolver()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 33664
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 33664
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 69793284352
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 69793284352
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_return:
// CHECK-NEXT: ret ptr @ftc._MaesMlse
// CHECK-NEXT: ret ptr @ftc._Msve2
// CHECK: resolver_else:
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 69793284352
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 69793284352
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 33664
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 33664
// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
// CHECK: resolver_return1:
// CHECK-NEXT: ret ptr @ftc._Msve2
// CHECK-NEXT: ret ptr @ftc._MaesMlse
// CHECK: resolver_else2:
// CHECK-NEXT: ret ptr @ftc.default
//
Expand Down Expand Up @@ -411,20 +411,20 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_cpu_features_resolver()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 70369817985280
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 70369817985280
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1125899906842624
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1125899906842624
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_return:
// CHECK-NEXT: ret ptr @ftc_inline3._MsbMsve
// CHECK-NEXT: ret ptr @ftc_inline3._Mbti
// CHECK: resolver_else:
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 1125899906842624
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 1125899906842624
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 70369817985280
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 70369817985280
// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
// CHECK: resolver_return1:
// CHECK-NEXT: ret ptr @ftc_inline3._Mbti
// CHECK-NEXT: ret ptr @ftc_inline3._MsbMsve
// CHECK: resolver_else2:
// CHECK-NEXT: ret ptr @ftc_inline3.default
//
Expand Down Expand Up @@ -521,20 +521,20 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
// CHECK-MTE-BTI-NEXT: resolver_entry:
// CHECK-MTE-BTI-NEXT: call void @__init_cpu_features_resolver()
// CHECK-MTE-BTI-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 33664
// CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 33664
// CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 69793284352
// CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 69793284352
// CHECK-MTE-BTI-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
// CHECK-MTE-BTI-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK-MTE-BTI: resolver_return:
// CHECK-MTE-BTI-NEXT: ret ptr @ftc._MaesMlse
// CHECK-MTE-BTI-NEXT: ret ptr @ftc._Msve2
// CHECK-MTE-BTI: resolver_else:
// CHECK-MTE-BTI-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-MTE-BTI-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 69793284352
// CHECK-MTE-BTI-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 69793284352
// CHECK-MTE-BTI-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 33664
// CHECK-MTE-BTI-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 33664
// CHECK-MTE-BTI-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
// CHECK-MTE-BTI-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
// CHECK-MTE-BTI: resolver_return1:
// CHECK-MTE-BTI-NEXT: ret ptr @ftc._Msve2
// CHECK-MTE-BTI-NEXT: ret ptr @ftc._MaesMlse
// CHECK-MTE-BTI: resolver_else2:
// CHECK-MTE-BTI-NEXT: ret ptr @ftc.default
//
Expand Down Expand Up @@ -868,20 +868,20 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
// CHECK-MTE-BTI-NEXT: resolver_entry:
// CHECK-MTE-BTI-NEXT: call void @__init_cpu_features_resolver()
// CHECK-MTE-BTI-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 70369817985280
// CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 70369817985280
// CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1125899906842624
// CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1125899906842624
// CHECK-MTE-BTI-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
// CHECK-MTE-BTI-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK-MTE-BTI: resolver_return:
// CHECK-MTE-BTI-NEXT: ret ptr @ftc_inline3._MsbMsve
// CHECK-MTE-BTI-NEXT: ret ptr @ftc_inline3._Mbti
// CHECK-MTE-BTI: resolver_else:
// CHECK-MTE-BTI-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-MTE-BTI-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 1125899906842624
// CHECK-MTE-BTI-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 1125899906842624
// CHECK-MTE-BTI-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 70369817985280
// CHECK-MTE-BTI-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 70369817985280
// CHECK-MTE-BTI-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
// CHECK-MTE-BTI-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
// CHECK-MTE-BTI: resolver_return1:
// CHECK-MTE-BTI-NEXT: ret ptr @ftc_inline3._Mbti
// CHECK-MTE-BTI-NEXT: ret ptr @ftc_inline3._MsbMsve
// CHECK-MTE-BTI: resolver_else2:
// CHECK-MTE-BTI-NEXT: ret ptr @ftc_inline3.default
//
Expand Down
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