Skip to content
/ VerilogProjects Public

All projects that utilize the Verilog & SystemVerilog HDL's.

3 stars 1 fork Branches Tags Activity
Star
Notifications You must be signed in to change notification settings

mankelly/VerilogProjects

BranchesTags

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 

History

131 Commits
16-bit Pipelined CPU
16-bit Pipelined CPU
 
 
8-bit CPU
8-bit CPU
 
 
Chasing LED Circuit
Chasing LED Circuit
 
 
EclypseZ7
EclypseZ7
 
 
Embedded FIFO Core
Embedded FIFO Core
 
 
FP Modules/Adder
FP Modules/Adder
 
 
Nexys Tetris
Nexys Tetris
 
 
SimpleProcessor
SimpleProcessor
 
 
UART Rx & Tx
UART Rx & Tx
 
 
README.md
README.md
 
 

Repository files navigation

VerilogProjects

Above are my projects that involve Verilog & SystemVerilog.

Projects that I am currently working on:

  • 16-bit RISC single cycle CPU.
  • 32-bit RISC 5 stage pipelined CPU.

About

All projects that utilize the Verilog & SystemVerilog HDL's.

Topics

fpga embedded-systems verilog xilinx systemverilog system-on-chip

Resources

Readme
Activity

Stars

3 stars

Watchers

1 watching

Forks

1 fork
Report repository

Releases

No releases published

Packages

No packages published

Languages