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Allow partially connected vectors on port map in VHDL-2019 #2251

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Allow partially connected vectors on port map in VHDL-2019

Allow partially connected vectors on port map in VHDL-2019 #2251

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Job Run time
Ubuntu 20.04
20m 9s
Windows MSYS2
12m 44s
Mac OS
13m 53s
External Projects
4m 4s
VUnit
6m 21s
VESTs
1m 31s
OSVVM
0s
58m 42s