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Implement LCS2016_007 sequential block statements
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Original file line number | Diff line number | Diff line change |
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entity seqblock1 is | ||
end entity; | ||
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architecture test of seqblock1 is | ||
begin | ||
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process is | ||
variable a : natural; | ||
begin | ||
for i in 1 to 100 loop | ||
a := i; | ||
block is | ||
constant c : natural := a + 1; | ||
variable a : integer := 99; | ||
begin | ||
wait for 1 ns; | ||
assert c = i + 1; | ||
assert a = 99; | ||
end block; | ||
end loop; | ||
wait; | ||
end process; | ||
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end architecture; |
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-- https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/281 | ||
entity seqblock2 is | ||
end entity; | ||
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library ieee; | ||
use ieee.std_logic_1164.all; | ||
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architecture test of seqblock2 is | ||
signal x : std_logic_vector(1 to 3) := "ZZZ"; | ||
begin | ||
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process is | ||
begin | ||
for i in 1 to 3 loop | ||
block is | ||
constant c : natural := i; | ||
begin | ||
x(c) <= '1'; | ||
end block; | ||
end loop; | ||
wait; | ||
end process; | ||
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x(1) <= '0'; | ||
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process is | ||
begin | ||
wait for 1 ns; | ||
assert x = "X11"; | ||
wait; | ||
end process; | ||
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end architecture; |
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Original file line number | Diff line number | Diff line change |
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entity lcs2016_07 is | ||
end entity; | ||
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architecture test of lcs2016_07 is | ||
begin | ||
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p1: process is | ||
variable v : bit := '1'; | ||
begin | ||
b1: block is -- OK | ||
variable v : integer := 1; | ||
constant c : boolean := true; | ||
begin | ||
v := 6; | ||
end block b1; | ||
assert c; -- Error | ||
block is | ||
shared variable v : integer; -- Error | ||
begin | ||
end block; | ||
wait; | ||
end process; | ||
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end architecture; |
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