PSL assertions should not be postponed

src/rt/model.c

@@ -535,7 +535,7 @@ static void scope_for_block(rt_model_t *m, tree_t block, rt_scope_t *parent)
 
             p->wakeable.kind      = W_PROPERTY;
             p->wakeable.pending   = false;
-            p->wakeable.postponed = true;
+            p->wakeable.postponed = false;
             p->wakeable.delayed   = false;
 
             APUSH(s->properties, p);

test/regress/psl13.vhd

@@ -20,7 +20,7 @@ begin
     cgen: c <= seq_c(clk);
     dgen: d <= seq_d(clk);
 
-    -- psl default clock is clk'event;
+    -- psl default clock is clk'delayed(0 ns)'event;
 
     -- Should fail at: 3 ns and 7 ns
     -- psl asrt_1 : assert always {a;b} |=> {c;d};

test/regress/psl2.vhd

@@ -18,8 +18,7 @@ architecture psl of psl2 is
   signal clk : natural;
 
   -- All is sensitive to rising edge of clk
-  -- psl default clock is clk'event;
-
+  -- psl default clock is clk'delayed(0 ns)'event;
 begin
 
   clkgen: clk <= clk + 1 after 1 ns when clk < 5;

test/regress/psl3.vhd

@@ -22,7 +22,7 @@ architecture psl of psl3 is
   signal clk : natural;
 
   -- All is sensitive to rising edge of clk
-  default clock is clk'event;
+  default clock is clk'delayed(0 ns)'event;
 
 begin
 

test/regress/psl5.vhd

@@ -26,7 +26,7 @@ architecture psl of psl5 is
   signal clk : natural;
 
   -- All is sensitive to rising edge of clk
-  -- psl default clock is clk'event;
+  -- psl default clock is clk'delayed(0 ns)'event;
 
 begin
 

test/regress/psl6.vhd

@@ -28,7 +28,7 @@ architecture psl of psl6 is
   signal clk : natural;
 
   -- All is sensitive to rising edge of clk
-  -- psl default clock is clk'event;
+  -- psl default clock is clk'delayed(0 ns)'event;
 
 begin