Allow 'PATH_NAME, etc. on instance labels. Fixes #730

src/lower.c

@@ -1310,6 +1310,32 @@ static vcode_reg_t lower_name_attr(lower_unit_t *lu, tree_t ref,
          return lower_wrap_string(tb_get(tb));
       }
 
+   case T_INSTANCE:
+      {
+         ident_t dname = tree_ident(decl);
+         lower_unit_t *it;
+         for (it = lu; it != NULL; it = it->parent) {
+            if (tree_ident(it->container) == dname)
+               break;
+         }
+
+         if (it == NULL)
+            fatal_trace("cannot find instance %s", istr(tree_ident(decl)));
+
+         LOCAL_TEXT_BUF tb = tb_new();
+
+         tree_t hier = tree_decl(it->container, 0);
+         assert(tree_kind(hier) == T_HIER);
+
+         if (which == ATTR_PATH_NAME)
+            tb_istr(tb, tree_ident(hier));
+         else
+            tb_istr(tb, tree_ident2(hier));
+
+         tb_append(tb, ':');
+         return lower_wrap_string(tb_get(tb));
+      }
+
    case T_BLOCK:
    case T_ENTITY:
    case T_ARCH:

src/parse.c

@@ -9772,6 +9772,9 @@ static tree_t p_component_instantiation_statement(ident_t label, tree_t name)
    if (spec != NULL)
       tree_set_spec(t, spec);
 
+   if (label != NULL)
+      insert_name(nametab, t, NULL);
+
    push_scope(nametab);
 
    if (peek() == tGENERIC)
@@ -9793,9 +9796,6 @@ static tree_t p_component_instantiation_statement(ident_t label, tree_t name)
    sem_check(t, nametab);
    pop_scope(nametab);
 
-   if (label)
-      insert_name(nametab, t, NULL);
-
    return t;
 }
 

src/sem.c

@@ -3651,6 +3651,7 @@ static bool sem_is_named_entity(tree_t t)
    case T_FILE_DECL:    case T_CONST_DECL:   case T_FUNC_DECL:
    case T_FUNC_BODY:    case T_PROC_DECL:    case T_PROC_BODY:
    case T_PROCESS:      case T_GENERIC_DECL: case T_PARAM_DECL:
+   case T_INSTANCE:
       return true;
    case T_IMPLICIT_SIGNAL:
       return tree_subkind(decl) == IMPLICIT_GUARD;   // See LRM 93 section 4.3
@@ -4951,11 +4952,18 @@ static bool sem_globally_static(tree_t t)
    }
 
    if (kind == T_ATTR_REF) {
+      const attr_kind_t predef = tree_subkind(t);
+
+      // A predefined attribute that is one of 'SIMPLE_NAME,
+      // 'INSTANCE_NAME, or 'PATH_NAME
+      if (predef == ATTR_SIMPLE_NAME || predef == ATTR_INSTANCE_NAME
+          || predef == ATTR_PATH_NAME)
+         return true;   // Clause j
+
       // A predefined attribute other than those listed below whose
       // prefix is either a globally static subtype or is an object or
       // function call that is of a globally static subtype, or in 2008,
       // a prefix which is a appropriate for a globally static attribute
-      const attr_kind_t predef = tree_subkind(t);
       if (predef == ATTR_EVENT || predef == ATTR_ACTIVE
           || predef == ATTR_LAST_EVENT || predef == ATTR_LAST_ACTIVE
           || predef == ATTR_LAST_VALUE || predef == ATTR_DRIVING

test/regress/gold/issue730.txt

@@ -0,0 +1 @@
+15ns+0: Report Note: :issue730:test_mod:

test/regress/issue730.vhd

@@ -0,0 +1,63 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity module_ref_label is
+    generic (
+        G_PATH : string := "None"
+    );
+    port (
+        clk   : in std_logic;
+        print : in std_logic
+    );
+end entity module_ref_label;
+
+architecture rtl of module_ref_label is
+
+begin
+    process (clk)
+    begin
+        if rising_edge(clk) then
+            if print = '1' then
+                report G_PATH;
+            end if;
+        end if;
+    end process;
+
+end architecture;
+
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use std.env.finish;
+
+entity issue730 is
+end entity issue730;
+
+architecture sim of issue730 is
+    signal clk : std_logic := '0';
+    signal print : std_logic;
+begin
+    clk <= not clk after 5 ns;
+
+    test_mod : entity work.module_ref_label
+    generic map (
+        G_PATH => test_mod'path_name
+    )
+    port map(
+        clk => clk,
+        print => print
+    );
+
+    test_proc : process is
+    begin
+        report test_proc'path_name;
+        wait until rising_edge(clk);
+        print <= '1';
+        wait until rising_edge(clk);
+        print <= '0';
+        finish;
+        wait;
+    end process;
+end architecture;