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VHDL2019 assert api - partial (#748)
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Original file line number | Diff line number | Diff line change |
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entity assert8 is | ||
end entity; | ||
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use std.env.all; | ||
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architecture test of assert8 is | ||
begin | ||
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process is | ||
begin | ||
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assert (IsVhdlAssertFailed = false); | ||
assert (IsVhdlAssertFailed(note) = false); | ||
assert (IsVhdlAssertFailed(warning) = false); | ||
assert (IsVhdlAssertFailed(error) = false); | ||
assert (IsVhdlAssertFailed(failure) = false); | ||
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assert (GetVhdlAssertCount = 0); | ||
assert (GetVhdlAssertCount(note) = 0); | ||
assert (GetVhdlAssertCount(warning) = 0); | ||
assert (GetVhdlAssertCount(error) = 0); | ||
assert (GetVhdlAssertCount(failure) = 0); | ||
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assert (False) report "First note" severity note; | ||
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assert (IsVhdlAssertFailed = false); | ||
assert (IsVhdlAssertFailed(note) = true); | ||
assert (IsVhdlAssertFailed(warning) = false); | ||
assert (IsVhdlAssertFailed(error) = false); | ||
assert (IsVhdlAssertFailed(failure) = false); | ||
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assert (GetVhdlAssertCount = 0); | ||
assert (GetVhdlAssertCount(note) = 1); | ||
assert (GetVhdlAssertCount(warning) = 0); | ||
assert (GetVhdlAssertCount(error) = 0); | ||
assert (GetVhdlAssertCount(failure) = 0); | ||
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assert (False) report "First warning" severity warning; | ||
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assert (IsVhdlAssertFailed = true); | ||
assert (IsVhdlAssertFailed(note) = true); | ||
assert (IsVhdlAssertFailed(warning) = true); | ||
assert (IsVhdlAssertFailed(error) = false); | ||
assert (IsVhdlAssertFailed(failure) = false); | ||
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assert (GetVhdlAssertCount = 1); | ||
assert (GetVhdlAssertCount(note) = 1); | ||
assert (GetVhdlAssertCount(warning) = 1); | ||
assert (GetVhdlAssertCount(error) = 0); | ||
assert (GetVhdlAssertCount(failure) = 0); | ||
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assert (False) report "First error" severity error; | ||
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assert (IsVhdlAssertFailed = true); | ||
assert (IsVhdlAssertFailed(note) = true); | ||
assert (IsVhdlAssertFailed(warning) = true); | ||
assert (IsVhdlAssertFailed(error) = true); | ||
assert (IsVhdlAssertFailed(failure) = false); | ||
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assert (GetVhdlAssertCount = 2); | ||
assert (GetVhdlAssertCount(note) = 1); | ||
assert (GetVhdlAssertCount(warning) = 1); | ||
assert (GetVhdlAssertCount(error) = 1); | ||
assert (GetVhdlAssertCount(failure) = 0); | ||
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assert (False) report "Second note" severity note; | ||
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assert (IsVhdlAssertFailed = true); | ||
assert (IsVhdlAssertFailed(note) = true); | ||
assert (IsVhdlAssertFailed(warning) = true); | ||
assert (IsVhdlAssertFailed(error) = true); | ||
assert (IsVhdlAssertFailed(failure) = false); | ||
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assert (GetVhdlAssertCount = 2); | ||
assert (GetVhdlAssertCount(note) = 2); | ||
assert (GetVhdlAssertCount(warning) = 1); | ||
assert (GetVhdlAssertCount(error) = 1); | ||
assert (GetVhdlAssertCount(failure) = 0); | ||
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assert (False) report "Second warning" severity warning; | ||
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assert (IsVhdlAssertFailed = true); | ||
assert (IsVhdlAssertFailed(note) = true); | ||
assert (IsVhdlAssertFailed(warning) = true); | ||
assert (IsVhdlAssertFailed(error) = true); | ||
assert (IsVhdlAssertFailed(failure) = false); | ||
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assert (GetVhdlAssertCount = 3); | ||
assert (GetVhdlAssertCount(note) = 2); | ||
assert (GetVhdlAssertCount(warning) = 2); | ||
assert (GetVhdlAssertCount(error) = 1); | ||
assert (GetVhdlAssertCount(failure) = 0); | ||
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assert (False) report "Second error" severity error; | ||
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assert (IsVhdlAssertFailed = true); | ||
assert (IsVhdlAssertFailed(note) = true); | ||
assert (IsVhdlAssertFailed(warning) = true); | ||
assert (IsVhdlAssertFailed(error) = true); | ||
assert (IsVhdlAssertFailed(failure) = false); | ||
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assert (GetVhdlAssertCount = 4); | ||
assert (GetVhdlAssertCount(note) = 2); | ||
assert (GetVhdlAssertCount(warning) = 2); | ||
assert (GetVhdlAssertCount(error) = 2); | ||
assert (GetVhdlAssertCount(failure) = 0); | ||
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report "Clearing VHDL asserts"; | ||
ClearVhdlAssert; | ||
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assert (IsVhdlAssertFailed = false); | ||
assert (IsVhdlAssertFailed(note) = false); | ||
assert (IsVhdlAssertFailed(warning) = false); | ||
assert (IsVhdlAssertFailed(error) = false); | ||
assert (IsVhdlAssertFailed(failure) = false); | ||
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assert (GetVhdlAssertCount = 0); | ||
assert (GetVhdlAssertCount(note) = 0); | ||
assert (GetVhdlAssertCount(warning) = 0); | ||
assert (GetVhdlAssertCount(error) = 0); | ||
assert (GetVhdlAssertCount(failure) = 0); | ||
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report "Note report" severity note; | ||
report "Warning report" severity warning; | ||
report "Error report" severity error; | ||
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assert (GetVhdlAssertCount = 2); | ||
assert (GetVhdlAssertCount(note) = 1); | ||
assert (GetVhdlAssertCount(warning) = 1); | ||
assert (GetVhdlAssertCount(error) = 1); | ||
assert (GetVhdlAssertCount(failure) = 0); | ||
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-- TODO: How to test failure severity when it always stops simulation? | ||
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finish; | ||
end process; | ||
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end architecture; |
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