Ibex to CVE2: necessary design and other coding modifications

[cairo-caplan]

I made a list of changes related to the remaining items of the transition from Ibex to CVE2 conversion #54.

1. Substituted references of the Ibex core to the CVE2, when it was due to.
2. Substituted references of "OpenHW Group" to "OpenHW Foundation" when due to, mainly on comments and documentation files.
3. Substituted references of "cv32e2" to "CV32E20" on documentation files.
4. Added the proper Eclipse Foundation copyright disclaimer for files modified this year (of 2025) and code files without a copyright disclaimer.
5. Removed unsupported or stripped-out configuration parameters from cve2_configs.yaml.
6. Substituted wrong FuseSoC- related references of lowrisc: cve2 to openhwgroup:cve2, as it is the practice for OpenHW's FuseSoC core files.
7. Disabled, by commenting out, the build-simple-system build-arty-100, build-csr-test, build-simple-system make targets of the main Makefile file, as they were previously stripped out from the code.
8. Added a make sec target for the Sequential Equivalence Checking (SEC) script, and a general clean target.
9. There were 3 files on the repository that implemented a clock gate: bhv/cve2_sim_clock_gate.sv, rtl/cve2_clock_gating.v and syn/rtl/prim_clock_gating.v. I substituted them for rtl/cve2_clock_gate.sv only, keeping the disclaimer that it should not be used for actual physical synthesis (ASIC or FPGA).
10. Changed the RTL named assertions prefix from Ibex to CVE2.
11. Declared the RVFI instruction interface bus (rvfi_instr_if) of rtl/cve2_core.sv, so that it can be properly linted by Verilator. Not needed by the cv32e20-dv functional verification environment as this interface is bound to the testbench, which get its type by CORE-V-VERIF's uvma_rvfi_instr_if.sv.
12. For the same reasons, defined clknrst_if and rvfi_csr_if on rtl/cve2_cs_registers.sv.
13. Added void definitions of the DPI functions simutil_get_scramble_key and simutil_get_scramble_nonce, that are needed for the creation of a simulation model of the CVE2 model for the RISCV Compliance test on the rtl/cve2_if_stage.sv - a solution borrowed from Ibex's project.
14. Commented out the unused type regfile_e on rtl/cve2_pkg.sv, as we don't support multiple implementations of the Registers File.
15. Added a waiver on the tracer (simulation-only) file rtl/cve2_tracer.sv for decoded_str, data_accessed and insn_is_compressed as it not was passing linting because Verilator treated them as multidriven signals, instead of just programming variables.
16. Adapted the SEC main script scripts/sec/sec.sh to always use as work and output directory the path build/, as FuseSoC build do.
17. Removed unnecessary vendor/ patch files and commented out the lines used to reference them on vendor/lowrisc_ip.vendor.hjson.

I know this is a big list of changes, which are linked to each other in varying degrees. So, for that, I ask your patience and to test them locally as necessary. Naturally, I am happy to discuss each item.