Ibex to CVE2: necessary design and other coding modifications

Makefile

@@ -11,103 +11,110 @@ help:
 	@echo "or how to set-up the different environments."
 
 # Use a parallel run (make -j N) for a faster build
-build-all: build-riscv-compliance build-simple-system build-arty-100 \
-      build-csr-test
+# build-all: build-riscv-compliance build-simple-system build-arty-100 \
+#       build-csr-test
+build-all: build-riscv-compliance
 
 
 # RISC-V compliance
 .PHONY: build-riscv-compliance
 build-riscv-compliance:
 	fusesoc --cores-root=. run --target=sim --setup --build \
-		lowrisc:cve2:cve2_riscv_compliance \
+		openhwgroup:cve2:cve2_riscv_compliance \
 		$(FUSESOC_CONFIG_OPTS)
 
 
-# Simple system
-# Use the following targets:
-# - "build-simple-system"
-# - "run-simple-system"
-.PHONY: build-simple-system
-build-simple-system:
-	fusesoc --cores-root=. run --target=sim --setup --build \
-		lowrisc:cve2:cve2_simple_system \
-		$(FUSESOC_CONFIG_OPTS)
+# # Simple system
+# # Use the following targets:
+# # - "build-simple-system"
+# # - "run-simple-system"
+# .PHONY: build-simple-system
+# build-simple-system:
+# 	fusesoc --cores-root=. run --target=sim --setup --build \
+# 		openhwgroup:cve2:cve2_simple_system \
+# 		$(FUSESOC_CONFIG_OPTS)
 
-simple-system-program = examples/sw/simple_system/hello_test/hello_test.vmem
-sw-simple-hello: $(simple-system-program)
+# simple-system-program = examples/sw/simple_system/hello_test/hello_test.vmem
+# sw-simple-hello: $(simple-system-program)
 
-.PHONY: $(simple-system-program)
-$(simple-system-program):
-	cd examples/sw/simple_system/hello_test && $(MAKE)
+# .PHONY: $(simple-system-program)
+# $(simple-system-program):
+# 	cd examples/sw/simple_system/hello_test && $(MAKE)
 
-Vcve2_simple_system = \
-      build/lowrisc_cve2_cve2_simple_system_0/sim-verilator/Vcve2_simple_system
-$(Vcve2_simple_system):
-	@echo "$@ not found"
-	@echo "Run \"make build-simple-system\" to create the dependency"
-	@false
+# Vcve2_simple_system = \
+#       build/openhwgroup_cve2_cve2_simple_system_0/sim-verilator/Vcve2_simple_system
+# $(Vcve2_simple_system):
+# 	@echo "$@ not found"
+# 	@echo "Run \"make build-simple-system\" to create the dependency"
+# 	@false
 
-run-simple-system: sw-simple-hello | $(Vcve2_simple_system)
-	build/lowrisc_cve2_cve2_simple_system_0/sim-verilator/Vcve2_simple_system \
-		--raminit=$(simple-system-program)
+# run-simple-system: sw-simple-hello | $(Vcve2_simple_system)
+# 	build/openhwgroup_cve2_cve2_simple_system_0/sim-verilator/Vcve2_simple_system \
+# 		--raminit=$(simple-system-program)
 
 compile_verilator:
 	fusesoc --cores-root . run --no-export --target=lint --tool=verilator --setup --build openhwgroup:cve2:cve2_top:0.1 2>&1 | tee buildsim.log
 
-# Arty A7 FPGA example
-# Use the following targets (depending on your hardware):
-# - "build-arty-35"
-# - "build-arty-100"
-# - "program-arty"
-arty-sw-program = examples/sw/led/led.vmem
-sw-led: $(arty-sw-program)
+# # Arty A7 FPGA example
+# # Use the following targets (depending on your hardware):
+# # - "build-arty-35"
+# # - "build-arty-100"
+# # - "program-arty"
+# arty-sw-program = examples/sw/led/led.vmem
+# sw-led: $(arty-sw-program)
 
-.PHONY: $(arty-sw-program)
-$(arty-sw-program):
-	cd examples/sw/led && $(MAKE)
+# .PHONY: $(arty-sw-program)
+# $(arty-sw-program):
+# 	cd examples/sw/led && $(MAKE)
 
-.PHONY: build-arty-35
-build-arty-35: sw-led
-	fusesoc --cores-root=. run --target=synth --setup --build \
-		lowrisc:cve2:top_artya7 --part xc7a35ticsg324-1L
+# .PHONY: build-arty-35
+# build-arty-35: sw-led
+# 	fusesoc --cores-root=. run --target=synth --setup --build \
+# 		openhwgroup:cve2:top_artya7 --part xc7a35ticsg324-1L
 
-.PHONY: build-arty-100
-build-arty-100: sw-led
-	fusesoc --cores-root=. run --target=synth --setup --build \
-		lowrisc:cve2:top_artya7 --part xc7a100tcsg324-1
+# .PHONY: build-arty-100
+# build-arty-100: sw-led
+# 	fusesoc --cores-root=. run --target=synth --setup --build \
+# 		openhwgroup:cve2:top_artya7 --part xc7a100tcsg324-1
 
-.PHONY: program-arty
-program-arty:
-	fusesoc --cores-root=. run --target=synth --run \
-		lowrisc:cve2:top_artya7
+# .PHONY: program-arty
+# program-arty:
+# 	fusesoc --cores-root=. run --target=synth --run \
+# 		openhwgroup:cve2:top_artya7
 
 
 # Lint check
-.PHONY: lint-core-tracing
-lint-core-tracing:
-	fusesoc --cores-root . run --target=lint lowrisc:cve2:cve2_core_tracing \
+.PHONY: lint-top-tracing
+lint-top-tracing:
+	fusesoc --cores-root . run --target=lint openhwgroup:cve2:cve2_top_tracing \
+		$(FUSESOC_CONFIG_OPTS)
+
+# Lint check
+.PHONY: lint-top
+lint-top:
+	fusesoc --cores-root . run --target=lint openhwgroup:cve2:cve2_top \
 		$(FUSESOC_CONFIG_OPTS)
 
 
-# CS Registers testbench
-# Use the following targets:
-# - "build-csr-test"
-# - "run-csr-test"
-.PHONY: build-csr-test
-build-csr-test:
-	fusesoc --cores-root=. run --target=sim --setup --build \
-	      --tool=verilator lowrisc:cve2:tb_cs_registers
-Vtb_cs_registers = \
-      build/lowrisc_cve2_tb_cs_registers_0/sim-verilator/Vtb_cs_registers
-$(Vtb_cs_registers):
-	@echo "$@ not found"
-	@echo "Run \"make build-csr-test\" to create the dependency"
-	@false
-
-.PHONY: run-csr-test
-run-csr-test: | $(Vtb_cs_registers)
-	fusesoc --cores-root=. run --target=sim --run \
-	      --tool=verilator lowrisc:cve2:tb_cs_registers
+# # CS Registers testbench
+# # Use the following targets:c
+# # - "build-csr-test"
+# # - "run-csr-test"
+# .PHONY: build-csr-test
+# build-csr-test:
+# 	fusesoc --cores-root=. run --target=sim --setup --build \
+# 	      --tool=verilator openhwgroup:cve2:tb_cs_registers
+# Vtb_cs_registers = \
+#       build/openhwgroup_cve2_tb_cs_registers_0/sim-verilator/Vtb_cs_registers
+# $(Vtb_cs_registers):
+# 	@echo "$@ not found"
+# 	@echo "Run \"make build-csr-test\" to create the dependency"
+# 	@false
+
+# .PHONY: run-csr-test
+# run-csr-test: | $(Vtb_cs_registers)
+# 	fusesoc --cores-root=. run --target=sim --run \
+# 	      --tool=verilator openhwgroup:cve2:tb_cs_registers
 
 # Echo the parameters passed to fusesoc for the chosen CVE2_CONFIG
 .PHONY: test-cfg
@@ -117,3 +124,12 @@ test-cfg:
 .PHONY: python-lint
 python-lint:
 	$(MAKE) -C util lint
+
+# Sequential Equivalence Checking
+.PHONY: sec
+sec:
+	./scripts/sec/sec.sh -t yosys
+
+.PHONY: clean
+clean:
+	-rm -rf ./build ./formal/riscv-formal/build

README.md

@@ -1,9 +1,9 @@
-# OpenHW Group CORE-V CVE2 RISC-V IP
+# OpenHW Foundation CORE-V CVE2 RISC-V IP
 
-CVE2 is a class of 2-stage pipeline OpenHW Group cores. Currently, the only core in this class is the CV32E20.
+CVE2 is a class of 2-stage pipeline OpenHW Foundation cores. Currently, the only core in this class is the CV32E20.
 CV32E20 is a fork of the [Ibex](https://github.com/lowRISC/ibex) core.
-Differently to Ibex, cv32e2 will target low cost as originally intended in the [Zero-riscy](https://doi.org/10.1109/PATMOS.2017.8106976) project.
-The core will be made compatible with the OpenHW Group OBI protocol, it will use the same sleep unit of CV32E4 family, and it will achieve TRL5 with the industrial-level verification [core-v-verif](https://github.com/openhwgroup/core-v-verif).
+Differently to Ibex, CV32E20 will target low cost as originally intended in the [Zero-riscy](https://doi.org/10.1109/PATMOS.2017.8106976) project.
+The core will be made compatible with the OpenHW Foundation OBI protocol, it will use the same sleep unit of CV32E4 family, and it will achieve TRL5 with the industrial-level verification [core-v-verif](https://github.com/openhwgroup/core-v-verif).
 
 # CV32E20 RISC-V Core
 
@@ -21,15 +21,15 @@ pipeline.
 CV32E20 was initially developed as part of the [PULP platform](https://www.pulp-platform.org)
 under the name ["Zero-riscy"](https://doi.org/10.1109/PATMOS.2017.8106976), and has been
 contributed to [lowRISC](https://www.lowrisc.org) who maintains it and develops it further.
-It was further adopted by the OpenHW Group to work towards an improved industrialization
+It was further adopted by the OpenHW Foundation to work towards an improved industrialization use through extensive verification, with the aid of the [Core-V Verification](https://github.com/openhwgroup/cv32e20-dv) environment.
 
 ## Verification
 
 The verification environment for the CVE2 is _not_ in this Repository.  There is a small, simple testbench here which is
 useful for experimentation only and should not be used to validate any changes to the RTL prior to pushing to the master
 branch of this repo.
 
-The verification environment for this core as well as other cores in the OpenHW Group CORE-V family is at the
+The verification environment for this core as well as other cores in the OpenHW Foundation CORE-V family is at the
 [core-v-verif](https://github.com/openhwgroup/core-v-verif) repository on GitHub.
 
 The Makefiles supported in the **core-v-verif** project automatically clone the appropriate version of the **cve2** RTL sources.
@@ -39,7 +39,7 @@ The Makefiles supported in the **core-v-verif** project automatically clone the
 A changelog is generated automatically in the documentation from the individual pull requests.
 In order to enable automatic changelog generation within the documentation, the committer is required to label each pull request
 that touches any file in 'rtl' (or any of its subdirectories) with *Component:RTL* and label each pull request that touches any file in
-'docs' (or any of its subdirectories) with *Component:Doc*. Pull requests taht are not labeled or labeled with *ignore-for-release* are
+'docs' (or any of its subdirectories) with *Component:Doc*. Pull requests that are not labeled or labeled with *ignore-for-release* are
 ignored for the changelog generation.
 
 Only the person who actually performs the merge can add these labels (you need committer rights). The changelog flow only works if at most
@@ -100,8 +100,7 @@ please:
 * Split large contributions into smaller commits addressing individual changes or bug fixes. Do not
   mix unrelated changes into the same commit!
 * Do not mix updates within the 'rtl' directory with updates within the 'docs' directory into the same pull request.
-* Write meaningful commit messages. For more information, please check out the [the Ibex contribution
-  guide](https://github.com/lowrisc/ibex/blob/master/CONTRIBUTING.md).
+* Write meaningful commit messages. For more information, please check out the [CVE2 contribution guide](CONTRIBUTING.md).
 * If asked to modify your changes, do fix up your commits and rebase your branch to maintain a
   clean history.
 * If the PR gets accepted and merged into the **dev** branch, an action is triggered automatically to check whether the changes are logically equivalent to the frozen RTL on a given set of parameters. If the changes are logically equivalent, the **dev** branch is automatically merged into the **master** branch. Otherwise, we need to investigate manually. If a bug is found, thus the changes are not logically equivalent, we follow the procedure documented [here](https://docs.openhwgroup.org/projects/cv32e40p-user-manual/core_versions.html).

cv32e20_manifest.flist

@@ -1,5 +1,6 @@
 ///////////////////////////////////////////////////////////////////////////////
 //
+// Copyright (c) 2025 Eclipse Foundation
 // Copyright 2022 OpenHW Group
 //
 // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
@@ -60,4 +61,4 @@ ${DESIGN_RTL_DIR}/cve2_top.sv
 ${DESIGN_RTL_DIR}/cve2_top_tracing.sv
 ${DESIGN_RTL_DIR}/cve2_tracer.sv
 
-${DESIGN_RTL_DIR}/../bhv/cve2_sim_clock_gate.sv
+${DESIGN_RTL_DIR}/cve2_clock_gate.sv

cve2_configs.yaml

@@ -1,94 +1,20 @@
+# Copyright (c) 2025 Eclipse Foundation
 # Copyright lowRISC contributors.
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
-# Ibex configurations files, holds the parameter sets that are tested under CI.
+# CVE2 configurations files, holds the parameter sets that are tested under CI.
 # Each configuration must specify the same set of parameters
 
 # Two-stage pipeline without additional branch target ALU and 3 cycle multiplier
 # (4 cycles for mulh), resulting in 2 stall cycles for mul (3 for mulh)
 small:
+  MHPMCounterNum           : 10
+  MHPMCounterWidth         : 40
   RV32E                    : 0
   RV32M                    : "cve2_pkg::RV32MFast"
-  RV32B                    : "cve2_pkg::RV32BNone"
-  RegFile                  : "cve2_pkg::RegFileFF"
-  WritebackStage           : 0
-  PMPEnable                : 0
-  PMPGranularity           : 0
-  PMPNumRegions            : 4
-
-# Configuration to match that used in the OpenTitan project
-opentitan:
-  RV32E                    : 0
-  RV32M                    : "cve2_pkg::RV32MSingleCycle"
-  RV32B                    : "cve2_pkg::RV32BOTEarlGrey"
-  RegFile                  : "cve2_pkg::RegFileFF"
-  WritebackStage           : 1
-  PMPEnable                : 1
-  PMPGranularity           : 0
-  PMPNumRegions            : 16
-
-# ===============================
-# * EXPERIMENTAL CONFIGURATIONS *
-# ===============================
-
-# Three-stage pipeline with additional branch traget ALU and 1 cycle multiplier
-# (2 cycles for mulh) so mul does not stall (mulh stall 1 cycles). This is the
-# maximum performance configuration.
-experimental-maxperf:
-  RV32E                    : 0
-  RV32M                    : "cve2_pkg::RV32MSingleCycle"
-  RV32B                    : "cve2_pkg::RV32BNone"
-  RegFile                  : "cve2_pkg::RegFileFF"
-  WritebackStage           : 1
-  PMPEnable                : 0
-  PMPGranularity           : 0
-  PMPNumRegions            : 4
-
-# experimental-maxperf config above plus PMP enabled with 16 regions.
-experimental-maxperf-pmp:
-  RV32E                    : 0
-  RV32M                    : "cve2_pkg::RV32MSingleCycle"
-  RV32B                    : "cve2_pkg::RV32BNone"
-  RegFile                  : "cve2_pkg::RegFileFF"
-  WritebackStage           : 1
-  PMPEnable                : 1
-  PMPGranularity           : 0
-  PMPNumRegions            : 16
-
-# experimental-maxperf-pmp config above with balanced bitmanip extension
-experimental-maxperf-pmp-bmbalanced:
-  RV32E                    : 0
-  RV32M                    : "cve2_pkg::RV32MSingleCycle"
-  RV32B                    : "cve2_pkg::RV32BBalanced"
-  RegFile                  : "cve2_pkg::RegFileFF"
-  WritebackStage           : 1
-  PMPEnable                : 1
-  PMPGranularity           : 0
-  PMPNumRegions            : 16
-
-# experimental-maxperf-pmp config above with full bitmanip extension
-experimental-maxperf-pmp-bmfull:
-  RV32E                    : 0
-  RV32M                    : "cve2_pkg::RV32MSingleCycle"
-  RV32B                    : "cve2_pkg::RV32BFull"
-  RegFile                  : "cve2_pkg::RegFileFF"
-  WritebackStage           : 1
-  PMPEnable                : 1
-  PMPGranularity           : 0
-  PMPNumRegions            : 16
-
-# experimental-maxperf with branch predictor switched on. This exists to allow
-# easy use of Ibex with the branch predictor in particular for CI runs. The
-# branch predictor will be enabled in all the 'maxperf' configs after further
-# development.
-experimental-branch-predictor:
-  RV32E                    : 0
-  RV32M                    : "cve2_pkg::RV32MSingleCycle"
-  RV32B                    : "cve2_pkg::RV32BNone"
-  RegFile                  : "cve2_pkg::RegFileFF"
-  WritebackStage           : 1
-  PMPEnable                : 0
-  PMPGranularity           : 0
-  PMPNumRegions            : 4
+  # RV32B                    : "cve2_pkg::RV32BNone"
+  # PMPEnable                : 0
+  # PMPGranularity           : 0
+  # PMPNumRegions            : 4
 

cve2_core.core

@@ -1,9 +1,10 @@
 CAPI=2:
+# Copyright (c) 2025 Eclipse Foundation
 # Copyright lowRISC contributors.
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "openhwgroup:cve2:cve2_core:0.1"
-description: "Ibex CPU Core Components"
+description: "CVE2 CPU Core Components"
 
 filesets:
   files_rtl: