Added Xilinx BRAM Macro and changes to kernel

.gitignore

@@ -16,6 +16,7 @@ apps/mandelbrot/build/cast
 /tmp
 **/log/
 **/out/
+.vscode
 node_modules
 
 __pycache__

apps/calculator/fpga/src/calculator_kernel.tlv

@@ -1,12 +1,122 @@
-\m4_TLV_version 1d: tl-x.org
+\m4_TLV_version 1d --fmtFlatSignals --bestsv --noline: tl-x.org
 \SV
+// -----------------------------------------------------------------------------
+// Copyright (c) 2019, Steven F. Hoover
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+//     * Redistributions of source code must retain the above copyright notice,
+//       this list of conditions and the following disclaimer.
+//     * Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in the
+//       documentation and/or other materials provided with the distribution.
+//     * The name Steven F. Hoover
+//       may not be used to endorse or promote products derived from this software
+//       without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// -----------------------------------------------------------------------------
+
+
 m4+definitions(['
-   m4_include_url(['https://raw.githubusercontent.com/stevehoover/makerchip_examples/ceebf870862e222ebc6eaf92d5a7fb85a525d069/1st-claas_template_with_macros.tlv'])
+// --------------------------------------------------------------------
+//
+// A library file for developing FPGA kernels for use with 1st CLaaS
+// (https://github.com/stevehoover/1st-CLaaS)
+//
+// --------------------------------------------------------------------
+
+// 1st CLaaS imported from https://github.com/stevehoover/makerchip_examples/blob/master/1st-claas_template_with_macros.tlv
+
+// The 1st CLaaS kernel module definition.
+// This must be defined prior to any \TLV region, so \TLV macro syntax cannot be used - just raw m4.
+// $1: kernel name
+
+m4_define(['m4_kernel_module_def'], ['
+   module $1['']_kernel #(
+       parameter integer C_DATA_WIDTH = 512 // Data width of both input and output data
+   )
+   (
+       input wire                       clk,
+       input wire                       reset,
+       output wire                      in_ready,
+       input wire                       in_avail,
+       input wire  [C_DATA_WIDTH-1:0]   in_data,
+       input wire                       out_ready,
+       output wire                      out_avail,
+       output wire [C_DATA_WIDTH-1:0]   out_data
+   );
+'])
+
+// Makerchip module definition containing a testbench and instantiation of the custom kernel.
+// This must be defined prior to any \TLV region, so \TLV macro syntax cannot be used - just raw m4.
+// $1: kernel name
+// $2: (opt) passed statement
+// $3: (opt) failed statement
+
+m4_define(['m4_makerchip_module_with_random_kernel_tb'], [' m4_ifelse_block(M4_MAKERCHIP, 1, ['
+   // Makerchip interfaces with this module, coded in SV.
+   m4_makerchip_module
+      // Instantiate a 1st CLaaS kernel with random inputs.
+      logic [511:0] in_data = {2{RW_rand_vect[255:0]}};
+      logic in_avail = ^ RW_rand_vect[7:0];
+      logic out_ready = ^ RW_rand_vect[15:8];
+
+      $1['']_kernel kernel (
+            .*,  // clk, reset, and signals above
+            .in_ready(),  // Ignore blocking (inputs are random anyway).
+            .out_avail(),  // Outputs dangle.
+            .out_data()    //  "
+         );
+      $2
+      $3
+   endmodule
+m4_kernel_module_def($1)
+'], ['
+m4_kernel_module_def($1)
+'])
 '])
-m4_makerchip_module_with_random_kernel_tb(my, ['assign passed = cyc_cnt > 20;'])
+
+'])
+
+// (Finally, now in TLV-land)
+
+// The hookup of kernel module SV interface signals to TLV signals following flow library conventions.
+\TLV tlv_wrapper(|_in, @_in, |_out, @_out, /_trans)
+   m4_pushdef(['m4_trans_ind'], m4_ifelse(/_trans, [''], [''], ['   ']))
+   // The input interface hookup.
+   |_in
+      @_in
+         $reset = *reset;
+         `BOGUS_USE($reset)
+         $avail = *in_avail;
+         *in_ready = ! $blocked;
+         /trans
+      m4_trans_ind   $data[C_DATA_WIDTH-1:0] = *in_data;
+   // The output interface hookup.
+   |_out
+      @_out
+         $blocked = ! *out_ready;
+         *out_avail = $avail;
+         /trans
+      m4_trans_ind   *out_data = $data;
+
+
+\SV
+m4_makerchip_module_with_random_kernel_tb(calculator, ['assign passed = cyc_cnt > 20;']) // Provide the name the top module for 1st CLaaS in $3 param
 m4+definitions([''])  // A hack to reset line alignment to address the fact that the above macro is multi-line. 
 \TLV
-   // A default direct hookup from |in to |out.
+
    m4+tlv_wrapper(|in, @0, |out, @0, /trans)
    |in
       @0
@@ -66,6 +176,7 @@ m4+definitions([''])  // A hack to reset line alignment to address the fact that
          // Extract output data to the output field
          /trans@0$data = |in@1$output;
 
-   m4+rename_flow(/top, |in, @0, |out, @0, /trans)
 \SV
    endmodule
+
+

apps/mandelbrot/build/awsver.txt

@@ -0,0 +1,17 @@
+{
+  "accountId" : "903992718225",
+  "architecture" : "x86_64",
+  "availabilityZone" : "us-east-1d",
+  "billingProducts" : null,
+  "devpayProductCodes" : null,
+  "marketplaceProductCodes" : [ "3sppv90yg5o5uyuw20at6ywak" ],
+  "imageId" : "ami-0e560af290c745f5b",
+  "instanceId" : "i-06157a7afe221b791",
+  "instanceType" : "c4.2xlarge",
+  "kernelId" : null,
+  "pendingTime" : "2021-08-19T16:22:29Z",
+  "privateIp" : "172.31.23.12",
+  "ramdiskId" : null,
+  "region" : "us-east-1",
+  "version" : "2017-09-30"
+}

apps/mandelbrot/build/sdaccel.ini

@@ -0,0 +1,6 @@
+[Debug]
+profile = true
+timeline_trace = true
+data_transfer_trace=coarse
+stall_trace=all
+

apps/manycore/build/sdaccel.ini

@@ -0,0 +1,8 @@
+[Debug]
+profile = true
+timeline_trace = true
+data_transfer_trace=coarse
+stall_trace=all
+
+[Emulation]
+launch_waveform=batch

apps/manycore/client/html/index.html

@@ -35,6 +35,9 @@ <h2>Assembly Code</h2>
 <p>
   <button id="trace-button">Trace On</button>
 </p>
+<p>
+  <button id="reset-button">Reset</button>
+</p>
 <h2>Assembled Code</h2>
 <div id="assembled-code"></div>
 <h2>IMem Write Response</h2>

apps/manycore/client/js/manycore.js

@@ -178,6 +178,13 @@ class WARPV_Example {
         $('#trace-button').text("Trace Off");
       }
     });
+
+    $('#reset-button').click( (evt) => {
+        this.server.cleanKernel();
+        this.server.startKernel();
+        $('#reset-button').text("Reset");
+    });
+
   }
 
   assemble() {

apps/manycore/fpga/src/manycore_kernel.tlv

@@ -1,4 +1,4 @@
-\m4_TLV_version 1d --noline --debugSigs --compiler verilator: tl-x.org
+\m4_TLV_version 1d --fmtFlatSignals --debugSigs --bestsv --noline --compiler verilator: tl-x.org
 \SV
 // -----------------------------------------------------------------------------
 // Copyright (c) 2019, Steven F. Hoover
@@ -78,7 +78,7 @@ m4+definitions(['
    m4_def(EXT_M, 0)
    m4_def(EXT_F, 0)
    m4_def(EXT_B, 0)
-   m4_def(NUM_CORES, 5)
+   m4_def(NUM_CORES, 2)
    m4_def(NUM_VCS, 2)
    m4_def(NUM_PRIOS, 2)
    m4_def(MAX_PACKET_SIZE, 8)
@@ -331,7 +331,7 @@ m4+definitions([''])  // A hack to reset line alignment to address the fact that
                $addr[M4_IMEM_INDEX_RANGE] = $in_data[(1 * M4_INSTR_CNT) + M4_IMEM_INDEX_MAX:(1 * M4_INSTR_CNT)];
                $instr[M4_INSTR_RANGE] = $in_data[(3 * M4_INSTR_CNT) - 1: 2 * M4_INSTR_CNT];
 
-   /core[1:0]
+   /M4_CORE_HIER
       // Mux from |kernel_in1@1 and |fetch@M4_FETCH_STAGE. TODO: No exclusivity check.
       |imem
          @1

apps/vadd/build/sdaccel.ini

@@ -0,0 +1,6 @@
+[Debug]
+profile = true
+timeline_trace = true
+data_transfer_trace=coarse
+stall_trace=all
+

apps/warpv/build/sdaccel.ini

@@ -0,0 +1,6 @@
+[Debug]
+profile = true
+timeline_trace = true
+data_transfer_trace=coarse
+stall_trace=all
+

apps/warpv/client/html/index.html

@@ -35,6 +35,9 @@ <h2>Assembly Code</h2>
 <p>
   <button id="trace-button">Trace On</button>
 </p>
+<p>
+  <button id="reset-button">Reset</button>
+</p>
 <h2>Assembled Code</h2>
 <div id="assembled-code"></div>
 <h2>IMem Write Response</h2>

apps/warpv/client/js/warpv.js

@@ -178,6 +178,13 @@ class WARPV_Example {
         $('#trace-button').text("Trace Off");
       }
     });
+
+    $('#reset-button').click( (evt) => {
+        this.server.cleanKernel();
+        this.server.startKernel();
+        $('#reset-button').text("Reset");
+    });
+
   }
 
   assemble() {

apps/warpv/fpga/src/warpv_kernel.tlv

@@ -1,4 +1,4 @@
-\m4_TLV_version 1d --noline --debugSigs: tl-x.org
+\m4_TLV_version 1d --fmtFlatSignals --bestsv --noline: tl-x.org
 \SV
 // -----------------------------------------------------------------------------
 // Copyright (c) 2019, Steven F. Hoover
@@ -103,7 +103,7 @@ m4+definitions(['
    m4_def(MEM_WR_STAGE, 3)
    m4_def(LD_RETURN_ALIGN, 4)
 
-   m4_define(['M4_XILINX'], 0)
+   m4_define(['M4_XILINX'], 1)
 
    m4_include_url(['https://raw.githubusercontent.com/stevehoover/tlv_flow_lib/7a2b37cc0ccd06bc66984c37e17ceb970fd6f339/pipeflow_lib.tlv'])
    m4_include_lib(['https://raw.githubusercontent.com/stevehoover/tlv_flow_lib/5a8c0387be80b2deccfcd1506299b36049e0663e/arrays.tlv'])
@@ -215,7 +215,71 @@ m4_kernel_module_def($1)
                // IMem
                $raw[M4_INSTR_RANGE] = /top|imem>>m4_align(2, M4_FETCH_STAGE + 1)$rd_instr;
 
-
+\TLV xilinx_bram(data_width, $_wrdata, $_wraddr, $_wren, $_rddata, $_rden, $_rdaddr)
+   m4_pushdef(['m4_we'], m4_ifelse(m4_eval(data_width > 36), 1, 8, m4_eval(data_width > 18), 1, 4, m4_eval(data_width > 9), 1, 2, 1))
+   \SV_plus
+      logic dbiterrb, sbiterrb, injectdbiterra, injectsbiterra, regceb, sleep, wea;
+      xpm_memory_sdpram #(
+         .ADDR_WIDTH_A(32),               // DECIMAL
+         .ADDR_WIDTH_B(32),               // DECIMAL
+         .AUTO_SLEEP_TIME(0),            // DECIMAL
+         .BYTE_WRITE_WIDTH_A(32),        // DECIMAL
+         .CLOCKING_MODE("common_clock"), // String
+         .ECC_MODE("no_ecc"),            // String
+         .MEMORY_INIT_FILE("none"),      // String
+         .MEMORY_INIT_PARAM("0"),        // String
+         .MEMORY_OPTIMIZATION("true"),   // String
+         .MEMORY_PRIMITIVE("block"),      // String
+         .MEMORY_SIZE(1024),             // DECIMAL
+         .MESSAGE_CONTROL(1),            // DECIMAL
+         .READ_DATA_WIDTH_B(32),         // DECIMAL
+         .READ_LATENCY_B(1),             // DECIMAL
+         .READ_RESET_VALUE_B("0"),       // String
+         .RST_MODE_A("SYNC"),            // String
+         .RST_MODE_B("SYNC"),            // String
+         .USE_EMBEDDED_CONSTRAINT(0),    // DECIMAL
+         .USE_MEM_INIT(0),               // DECIMAL
+         .WAKEUP_TIME("disable_sleep"),  // String
+         .WRITE_DATA_WIDTH_A(32),        // DECIMAL
+         .WRITE_MODE_B("no_change")      // String
+      )   xpm_memory_sdpram_inst (
+         .dbiterrb(dbiterrb),             // 1-bit output: Status signal to indicate double bit error occurrence
+                                          // on the data output of port B.
+         .doutb(>>1$['']$_rddata),                   // READ_DATA_WIDTH_B-bit output: Data output for port B read operations.
+         .sbiterrb(sbiterrb),             // 1-bit output: Status signal to indicate single bit error occurrence
+                                          // on the data output of port B.
+         .addra($_wraddr),                   // ADDR_WIDTH_A-bit input: Address for port A write operations.
+         .addrb($_rdaddr),                   // ADDR_WIDTH_B-bit input: Address for port B read operations.
+         .clka(*clk),                     // 1-bit input: Clock signal for port A. Also clocks port B when
+                                          // parameter CLOCKING_MODE is "common_clock".
+         .clkb(*clk),                     // 1-bit input: Clock signal for port B when parameter CLOCKING_MODE is
+                                          // "independent_clock". Unused when parameter CLOCKING_MODE is
+                                          // "common_clock"
+         .dina($_wrdata),                     // WRITE_DATA_WIDTH_A-bit input: Data input for port A write operations.
+         .ena($_wren),                       // 1-bit input: Memory enable signal for port A. Must be high on clock
+                                          // cycles when write operations are initiated. Pipelined internally.
+         .enb($_rden),                       // 1-bit input: Memory enable signal for port B. Must be high on clock
+                                          // cycles when read operations are initiated. Pipelined internally.
+         .injectdbiterra(1'b0), // 1-bit input: Controls double bit error injection on input data when
+                                          // ECC enabled (Error injection capability is not available in
+                                          // "decode_only" mode).
+         .injectsbiterra(1'b0), // 1-bit input: Controls single bit error injection on input data when
+                                          // ECC enabled (Error injection capability is not available in
+                                          // "decode_only" mode).
+         .regceb(1'b1),                 // 1-bit input: Clock Enable for the last register stage on the output
+                                          // data path.
+         .rstb(*reset),                     // 1-bit input: Reset signal for the final port B output register stage.
+                                          // Synchronously resets output port doutb to the value specified by
+                                          // parameter READ_RESET_VALUE_B.
+         .sleep(1'b0),                   // 1-bit input: sleep signal to enable the dynamic power saving feature.
+         .wea(1'b1)                        // WRITE_DATA_WIDTH_A-bit input: Write enable vector for port A input
+                                          // data port dina. 1 bit wide when word-wide writes are used. In
+                                          // byte-wide write configurations, each bit controls the writing one
+                                          // byte of dina to address addra. For example, to synchronously write
+                                          // only bits [15-8] of dina when WRITE_DATA_WIDTH_A is 32, wea would be
+                                          // 4'b0010.
+      );
+
 \SV
 m4_makerchip_module_with_random_kernel_tb(warpv, ['assign passed = cyc_cnt > 20;']) // Provide the name the top module for 1st CLaaS in $3 param
 m4+definitions([''])  // A hack to reset line alignment to address the fact that the above macro is multi-line. 
@@ -317,7 +381,7 @@ m4+definitions([''])  // A hack to reset line alignment to address the fact that
    |imem
       @1
          // TODO: I'm not sure about the timing. I'm assuming inputs are a cycle before outputs.
-         m4+bram_sdp(M4_INSTR_CNT, $instr, $addr, $wr_en, $rd_instr[M4_INSTR_RANGE], $accepted && $rd_en, $addr)
+         m4+xilinx_bram(M4_INSTR_CNT, $instr, $addr, $wr_en, $rd_instr[M4_INSTR_RANGE], $accepted && $rd_en, $addr)
    '])
    // Recirculate rd_data (as the bp_pipeline would naturally have done the cycle before).
    |kernel2
@@ -347,3 +411,4 @@ m4+definitions([''])  // A hack to reset line alignment to address the fact that
 \SV
    endmodule
 
+