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Bug/eda 3326/pll clk handling #818

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Merged
merged 4 commits into from
Nov 18, 2024
Merged

Bug/eda 3326/pll clk handling #818

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55e1384
Stopping pass through LUT creation for PLL_CLK signal on output primi…
behzadmehmood Nov 17, 2024
e81065c
Merge branch 'main' of https://github.com/os-fpga/yosys_verific_rs in…
behzadmehmood Nov 17, 2024
2d196a5
Incremented patch version
behzadmehmood Nov 17, 2024
64e1390
Incremented patch version
behzadmehmood Nov 18, 2024
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2 changes: 1 addition & 1 deletion CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,7 @@ set(VERSION_MINOR 0)



set(VERSION_PATCH 380)
set(VERSION_PATCH 381)



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15 changes: 9 additions & 6 deletions design_edit/src/rs_design_edit.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -1000,8 +1000,9 @@ struct DesignEditRapidSilicon : public ScriptPass {
if (std::find(io_prim_wires.begin(), io_prim_wires.end(), bit.wire->name.str()) !=
io_prim_wires.end()) {
if (cell->input(portName) &&
portName.str() != "\\CLK_IN" &&
portName.str() != "\\C" &&
portName != RTLIL::escape_id("CLK_IN") &&
portName != RTLIL::escape_id("C") &&
portName != RTLIL::escape_id("PLL_CLK") &&
(is_out_prim || is_intf_prim)) {
if (unset_port)
{
Expand Down Expand Up @@ -1574,8 +1575,9 @@ struct DesignEditRapidSilicon : public ScriptPass {
process_wire(cell, portName, wire);
if (is_out_prim || is_intf_prim) {
if (cell->input(portName)) {
if (portName.str() != "\\CLK_IN" &&
portName.str() != "\\C")
if (portName != RTLIL::escape_id("CLK_IN") &&
portName != RTLIL::escape_id("C") &&
portName != RTLIL::escape_id("PLL_CLK"))
out_prim_ins.insert(wire->name.str());
}
}
Expand All @@ -1596,8 +1598,9 @@ struct DesignEditRapidSilicon : public ScriptPass {
process_wire(cell, portName, wire);
if (is_out_prim || is_intf_prim) {
if (cell->input(portName)) {
if (portName.str() != "\\CLK_IN" &&
portName.str() != "\\C")
if (portName != RTLIL::escape_id("CLK_IN") &&
portName != RTLIL::escape_id("C") &&
portName != RTLIL::escape_id("PLL_CLK"))
out_prim_ins.insert(wire->name.str());
}
}
Expand Down