GitHub - pawlex/uart: verilog uart model with AXI interface. No FIFIO

pawlex / uart Public

generated from pawlex/verilog_simulate

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verilog uart model with AXI interface. No FIFIO

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Name		Name	Last commit message	Last commit date
Latest commit History 7 Commits
bin		bin
.gitignore		.gitignore
.gtkwaverc		.gtkwaverc
README.md		README.md
compile		compile
tb.v		tb.v
top.v		top.v
uart.v		uart.v
uart_loopback.png		uart_loopback.png
uart_rx.v		uart_rx.v
uart_tx.v		uart_tx.v

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UART with AXI interface and simulation environment

Components

uart.v - top level
uart_tx.v - tx side
uart_rx.v - rx side
tb.v - test bench

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verilog uart model with AXI interface. No FIFIO

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