Merge pull request #18 from saurabhsingh99100/dev

Dev

Makefile

@@ -175,6 +175,7 @@ $(bin_dir)/$(sim_executable): $(vobject_dir)/V$(verilog_topmodule)__ALLcls.o $(v
 #~	scar		:	verify using scar
 .PHONY: scar
 scar: $(bin_dir)/$(sim_executable)
+	@echo ">> Running SCAR"
 	cd test/scar/ && make
 
 

README.md

@@ -154,7 +154,7 @@ just replace `your_path` with the path to the `riscv-atom/build/bin` directory o
 
 ### Running example programs
 
-Example programs reside in the `sw/examples` directory. Each folderr inside this directory contains an example  C/Assembly program and a shell script to compile it.
+Example programs reside in the `sw/examples` directory. Each folder inside this directory contains an example  C/Assembly program and a shell script to compile it.
 
 Let's try the banner program, Go to the banner directory
 

Trace_AtomBones.gtkw

@@ -0,0 +1,70 @@
+[*]
+[*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI
+[*] Mon Jul 19 21:11:30 2021
+[*]
+[dumpfile] "/home/frozenalpha/git/riscv/riscv-atom/build/trace/trace.vcd"
+[dumpfile_mtime] "Mon Jul 19 20:03:50 2021"
+[dumpfile_size] 22256
+[savefile] "/home/frozenalpha/git/riscv/riscv-atom/Trace_AtomBones.gtkw"
+[timestart] 184
+[size] 1600 871
+[pos] -1 -1
+*-3.759334 563 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] TOP.
+[treeopen] TOP.AtomBones.
+[treeopen] TOP.AtomBones.atom_core.
+[sst_width] 212
+[signals_width] 230
+[sst_expanded] 1
+[sst_vpaned_height] 238
+@29
+[color] 1
+TOP.clk_i
+[color] 1
+TOP.rst_i
+@200
+-IBUS
+@22
+[color] 2
+TOP.imem_addr_o[31:0]
+@28
+[color] 2
+TOP.dmem_valid_o
+@22
+[color] 2
+TOP.imem_data_i[31:0]
+@28
+[color] 2
+TOP.imem_ack_i
+@200
+-DBUS
+@22
+[color] 3
+TOP.dmem_addr_o[31:0]
+[color] 3
+TOP.dmem_data_o[31:0]
+[color] 3
+TOP.dmem_sel_o[3:0]
+@28
+[color] 3
+TOP.dmem_we_o
+[color] 3
+TOP.dmem_valid_o
+@22
+[color] 3
+TOP.dmem_data_i[31:0]
+@28
+[color] 3
+TOP.dmem_ack_i
+@200
+-CORE
+@22
+TOP.AtomBones.atom_core.ProgramCounter[31:0]
+TOP.AtomBones.atom_core.ProgramCounter_Old[31:0]
+TOP.AtomBones.atom_core.InstructionRegister[31:0]
+@28
+TOP.AtomBones.atom_core.stall_stage1
+TOP.AtomBones.atom_core.stall_stage2
+TOP.AtomBones.atom_core.insert_bubble
+[pattern_trace] 1
+[pattern_trace] 0

Trace_HydrogenSoC.gtkw

@@ -0,0 +1,84 @@
+[*]
+[*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI
+[*] Mon Jul 19 21:10:43 2021
+[*]
+[dumpfile] "/home/frozenalpha/git/riscv/riscv-atom/build/trace/trace.vcd"
+[dumpfile_mtime] "Mon Jul 19 20:03:50 2021"
+[dumpfile_size] 22256
+[savefile] "/home/frozenalpha/git/riscv/riscv-atom/Trace_HydrogenSoC.gtkw"
+[timestart] 569
+[size] 1600 871
+[pos] -1 -1
+*-3.848547 624 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] TOP.
+[treeopen] TOP.HydrogenSoC.
+[treeopen] TOP.HydrogenSoC.atom_wb_core.
+[treeopen] TOP.HydrogenSoC.atom_wb_core.atom_core.
+[sst_width] 212
+[signals_width] 230
+[sst_expanded] 1
+[sst_vpaned_height] 238
+@28
+[color] 1
+TOP.rst_i
+[color] 1
+TOP.clk_i
+@200
+-IBUS
+@22
+[color] 2
+TOP.HydrogenSoC.wb_ibus_adr_o[31:0]
+@28
+[color] 2
+TOP.HydrogenSoC.wb_ibus_stb_o
+@22
+[color] 2
+TOP.HydrogenSoC.wb_ibus_dat_i[31:0]
+@28
+[color] 2
+TOP.HydrogenSoC.wb_ibus_ack_i
+TOP.HydrogenSoC.atom_wb_core.atom_core.imem_handshake
+@200
+-DBUS
+@22
+[color] 3
+TOP.HydrogenSoC.wb_dbus_adr_o[31:0]
+@28
+[color] 3
+TOP.HydrogenSoC.wb_dbus_stb_o
+@22
+[color] 3
+TOP.HydrogenSoC.wb_dbus_sel_o[3:0]
+@28
+[color] 3
+TOP.HydrogenSoC.wb_dbus_we_o
+@22
+[color] 3
+TOP.HydrogenSoC.wb_dbus_dat_o[31:0]
+[color] 3
+TOP.HydrogenSoC.wb_dbus_dat_i[31:0]
+@28
+[color] 3
+TOP.HydrogenSoC.wb_dbus_ack_i
+TOP.HydrogenSoC.atom_wb_core.atom_core.dmem_handshake
+@200
+-CORE
+@22
+TOP.HydrogenSoC.atom_wb_core.atom_core.ProgramCounter[31:0]
+TOP.HydrogenSoC.atom_wb_core.atom_core.ProgramCounter_Old[31:0]
+TOP.HydrogenSoC.atom_wb_core.atom_core.InstructionRegister[31:0]
+@28
+TOP.HydrogenSoC.atom_wb_core.atom_core.ignore_imem_handshake
+TOP.HydrogenSoC.atom_wb_core.atom_core.jump_decision
+TOP.HydrogenSoC.atom_wb_core.atom_core.stall_stage1
+TOP.HydrogenSoC.atom_wb_core.atom_core.stall_stage2
+TOP.HydrogenSoC.atom_wb_core.atom_core.insert_bubble
+TOP.HydrogenSoC.atom_wb_core.atom_core.d_rf_we
+TOP.HydrogenSoC.atom_wb_core.atom_core.rf.Data_We_i
+TOP.HydrogenSoC.atom_wb_core.atom_core.d_rf_din_sel[2:0]
+@22
+TOP.HydrogenSoC.atom_wb_core.atom_core.rf.Data_i[31:0]
+TOP.HydrogenSoC.atom_wb_core.atom_core.rf.regs(3)[31:0]
+TOP.HydrogenSoC.atom_wb_core.atom_core.rf.regs(5)[31:0]
+[pattern_trace] 1
+[pattern_trace] 0

rtl/HydrogenSoC.v

@@ -7,7 +7,7 @@
 `include "core/AtomRV_wb.v"
 
 /**
- *  Hydogen SoC
+ *  Hydrogen SoC
  *  Barebone SoC housing a single atom core, imem, & dmem.
  */
 

rtl/core/Alu.v

@@ -3,7 +3,7 @@
 //
 //  File : Alu.v
 //
-//  Desciption : Arithmetic and logic unit for Atom core
+//  Description : Arithmetic and logic unit for Atom core
 ////////////////////////////////////////////////////////////////////
 `default_nettype none
 
@@ -18,6 +18,8 @@ module Alu
     output reg [31:0] Out
 );
 
+wire signed [31:0] A_s = A;
+
 always @(*) begin
     case(Sel)
 
@@ -26,9 +28,9 @@ always @(*) begin
     `__ALU_XOR__:   Out = A ^ B;
     `__ALU_OR__ :   Out = A | B;
     `__ALU_AND__:   Out = A & B;
-    `__ALU_SLL__:   Out = A << B;
-    `__ALU_SRL__:   Out = A >> B;
-    `__ALU_SRA__:   Out = A >>> B;
+    `__ALU_SLL__:   Out = A << B[4:0];
+    `__ALU_SRL__:   Out = A >> B[4:0];
+    `__ALU_SRA__:   Out = A_s >>> B[4:0];
 
     default:    Out = 32'd0;
     endcase