Reduce warnings

sy2002 · Jan 6, 2024 · f0ef9da · f0ef9da
1 parent 8e9db8f
commit f0ef9da
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Showing 4 changed files with 14 additions and 11 deletions.
diff --git a/CORE/vhdl/clk.vhd b/CORE/vhdl/clk.vhd
@@ -115,7 +115,7 @@ begin
    i_xpm_cdc_async_rst_main : xpm_cdc_async_rst
       generic map (
          RST_ACTIVE_HIGH => 1,
-         DEST_SYNC_FF    => 10
+         DEST_SYNC_FF    => 6
       )
       port map (
          src_arst  => not main_locked,   -- 1-bit input: Source reset signal.

diff --git a/M2M/common.xdc b/M2M/common.xdc
@@ -79,7 +79,8 @@ create_generated_clock -name div_clk -source [get_ports {clk_i}] -divide_by 2 [g
 set_case_analysis 1 [get_pins i_framework/i_video_out_clock/clk_mux_reg/Q]
 
 ## Generic CDC
-set_max_delay 8 -datapath_only -from [get_clocks] -to [get_pins -hierarchical "*cdc_stable_gen.dst_*_d_reg[*]/D"]
+set_max_delay 8 -datapath_only -from [get_generated_clocks] -to [get_pins -hierarchical "*cdc_stable_gen.dst_*_d_reg[*]/D"]
+set_max_delay 8 -datapath_only -from [get_clocks clk] -to [get_pins -hierarchical "*cdc_stable_gen.dst_*_d_reg[*]/D"]
 
 ## QNICE's EAE combinatorial division networks take longer than the regular clock period, so we specify a multicycle path
 ## see also the comments in EAE.vhd and explanations in UG903/chapter 5/Multicycle Paths as well as ug911/page 25

diff --git a/M2M/vhdl/av_pipeline/vga_osm.vhd b/M2M/vhdl/av_pipeline/vga_osm.vhd
@@ -70,13 +70,15 @@ architecture synthesis of vga_osm is
       vga_osm_rgb         : std_logic_vector(23 downto 0);
    end record stage_t;
 
-   signal stage1 : stage_t;
-   signal stage2 : stage_t;
-   signal stage3 : stage_t;
-   signal stage4 : stage_t;
-   signal stage5 : stage_t;
-   signal stage6 : stage_t;
-   signal stage7 : stage_t;
+   constant STATE_INIT : stage_t := (0,0,0,0,0,0,0,0,0,0,0,0,0,X"0000",X"00",'0',X"000000");
+
+   signal stage1 : stage_t := STATE_INIT;
+   signal stage2 : stage_t := STATE_INIT;
+   signal stage3 : stage_t := STATE_INIT;
+   signal stage4 : stage_t := STATE_INIT;
+   signal stage5 : stage_t := STATE_INIT;
+   signal stage6 : stage_t := STATE_INIT;
+   signal stage7 : stage_t := STATE_INIT;
    signal stage5_vga_osm_font_addr : std_logic_vector(11 downto 0);
    signal stage5_vga_osm_vram_attr : std_logic_vector( 7 downto 0);
    signal stage6_vga_osm_font_data : std_logic_vector(15 downto 0);

diff --git a/M2M/vhdl/clk_m2m.vhd b/M2M/vhdl/clk_m2m.vhd
@@ -180,7 +180,7 @@ begin
    i_xpm_cdc_async_rst_hr : xpm_cdc_async_rst
       generic map (
          RST_ACTIVE_HIGH => 1,
-         DEST_SYNC_FF    => 10
+         DEST_SYNC_FF    => 6
       )
       port map (
          -- 1-bit input: Source reset signal
@@ -196,7 +196,7 @@ begin
    i_xpm_cdc_async_rst_audio : xpm_cdc_async_rst
       generic map (
          RST_ACTIVE_HIGH => 1,
-         DEST_SYNC_FF    => 10
+         DEST_SYNC_FF    => 6
       )
       port map (
          src_arst  => not (audio_locked and sys_rstn_i),   -- 1-bit input: Source reset signal.