Examples for the Terasic DE0-nano-SOC board
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Updated
Mar 30, 2018 - Makefile
Examples for the Terasic DE0-nano-SOC board
Solutions to coursework Nand2Tetris by Shimon Schocken and Noam Nisan https://www.nand2tetris.org/
Verilog implementations of different simple tasks
Resolución de laboratorios y guías prácticas asignadas en el curso de Diseño Digital Avanzado 2022.
👾 My studies with Verilog and notions of digital systems.
Racket-based hardware definition DSL for generating gateware for FPGAs, ASICs and the like
A package for Sublime Text that creates a project outline for a VHDL/Verilog HDL source code tree
This repository contains my work (only the hdl files) in completing the project based course Nand2Tetris on Coursera offered by the Hebrew University of Jerusalem. In this project, a basic CPU comprising of a functional ALU is designed starting from the very basic NAND gate.
simple demo hardware code for implement access to ST7789 LCD display from FPGA
Implementation of one-level cache memory for CPU, written on SystemVerilog
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