HDL libraries and projects

Sol-1: A CPU/Computer System made from 74 series logic.

An agile package manager and extensible build tool for HDLs

A toolbox for automating some of the more tedious refactoring tasks comming with common HDL languages (VHDL/Verilog). Including among others: entity to instance conversion and entity cross language conversion.

A simple tool that can be used to convert the header syntax of a verilog module or VHDL entity to an instantiation syntax and create testbench structures (top level and verify). The project is aimed at removing the need for tedious refactoring of module headers when instantiating modules or verifying individual modules with testbenches.

The HDL Bits Solutions repository provides answers to the HDL Bits exercises, which are designed for practicing digital hardware design using Verilog HDL. Join us to learn, share, and master digital design!

A modern hardware definition language and toolchain based on Python

A go-to repository for exploring, learning, and mastering RTL design and verification.

🔥🔥🔥 A collection of some awesome public NVIDIA CUDA, cuBLAS, cuDNN, TensorRT, AMD ROCm and FPGA projects.

Playground for VGA projects on Tiny Tapeout

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

A web-based IDE for https://nand2tetris.org

🧩 Monibuca is a Modularized, Extensible framework for building Streaming Server

Synthesize Verilog to Minecraft redstone

A 32-bit CPU being developed in SpinalHDL

DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language

The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.

A huge VHDL library for FPGA development

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

Test suite designed to check compliance with the SystemVerilog standard.