Fix some SRAM pin sizes/locations (#688)

* fix some SRAM pin sizes/locations * don't update GDSs that weren't changed
ucb-bar · Dec 14, 2022 · 0e1b156 · 0e1b156
1 parent a4d1fd5
commit 0e1b156
Show file tree

Hide file tree

Showing 8 changed files with 569 additions and 565 deletions.
diff --git a/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW256x128_x4.gds b/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW256x128_x4.gds
diff --git a/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW256x64_x4.gds b/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW256x64_x4.gds
diff --git a/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW32x33_x4.gds b/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW32x33_x4.gds
diff --git a/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW32x39_x4.gds b/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW32x39_x4.gds
diff --git a/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW256x128_x4.lef b/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW256x128_x4.lef
diff --git a/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW256x64_x4.lef b/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW256x64_x4.lef
diff --git a/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW32x33_x4.lef b/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW32x33_x4.lef
@@ -1031,230 +1031,232 @@ MACRO SRAM2RW32x33
     DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT 
+      LAYER M4 ;
+        RECT 0.0 29.088 4.0 29.184 ;
     END 
   END O2[4]
   PIN O2[5]
     DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT 
       LAYER M4 ;
-        RECT 0.0 29.088 4.0 29.184 ;
+        RECT 0.0 29.28 4.0 29.376 ;
     END 
   END O2[5]
   PIN O2[6]
     DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT 
       LAYER M4 ;
-        RECT 0.0 29.28 4.0 29.376 ;
+        RECT 0.0 29.472 4.0 29.568 ;
     END 
   END O2[6]
   PIN O2[7]
     DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT 
       LAYER M4 ;
-        RECT 0.0 29.472 4.0 29.568 ;
+        RECT 0.0 29.664 4.0 29.76 ;
     END 
   END O2[7]
   PIN O2[8]
     DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT 
       LAYER M4 ;
-        RECT 0.0 29.664 4.0 29.76 ;
+        RECT 0.0 29.856 4.0 29.952 ;
     END 
   END O2[8]
   PIN O2[9]
     DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT 
       LAYER M4 ;
-        RECT 0.0 29.856 4.0 29.952 ;
+        RECT 0.0 30.048 4.0 30.144 ;
     END 
   END O2[9]
   PIN O2[10]
     DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT 
       LAYER M4 ;
-        RECT 0.0 30.048 4.0 30.144 ;
+        RECT 0.0 30.24 4.0 30.336 ;
     END 
   END O2[10]
   PIN O2[11]
     DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT 
       LAYER M4 ;
-        RECT 0.0 30.24 4.0 30.336 ;
+        RECT 0.0 30.816 4.0 30.912 ;
     END 
   END O2[11]
   PIN O2[12]
     DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT 
       LAYER M4 ;
-        RECT 0.0 30.816 4.0 30.912 ;
+        RECT 0.0 31.008 4.0 31.104 ;
     END 
   END O2[12]
   PIN O2[13]
     DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT 
       LAYER M4 ;
-        RECT 0.0 31.008 4.0 31.104 ;
+        RECT 0.0 31.2 4.0 31.296 ;
     END 
   END O2[13]
   PIN O2[14]
     DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT 
       LAYER M4 ;
-        RECT 0.0 31.2 4.0 31.296 ;
+        RECT 0.0 31.392 4.0 31.488 ;
     END 
   END O2[14]
   PIN O2[15]
     DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT 
       LAYER M4 ;
-        RECT 0.0 31.392 4.0 31.488 ;
+        RECT 0.0 31.584 4.0 31.68 ;
     END 
   END O2[15]
   PIN O2[16]
     DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT 
       LAYER M4 ;
-        RECT 0.0 31.584 4.0 31.68 ;
+        RECT 0.0 31.776 4.0 31.872 ;
     END 
   END O2[16]
   PIN O2[17]
     DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT 
       LAYER M4 ;
-        RECT 0.0 31.776 4.0 31.872 ;
+        RECT 0.0 31.968 4.0 32.064 ;
     END 
   END O2[17]
   PIN O2[18]
     DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT 
       LAYER M4 ;
-        RECT 0.0 31.968 4.0 32.064 ;
+        RECT 0.0 32.16 4.0 32.256 ;
     END 
   END O2[18]
   PIN O2[19]
     DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT 
       LAYER M4 ;
-        RECT 0.0 32.16 4.0 32.256 ;
+        RECT 0.0 32.736 4.0 32.832 ;
     END 
   END O2[19]
   PIN O2[20]
     DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT 
       LAYER M4 ;
-        RECT 0.0 32.736 4.0 32.832 ;
+        RECT 0.0 32.928 4.0 33.024 ;
     END 
   END O2[20]
   PIN O2[21]
     DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT 
       LAYER M4 ;
-        RECT 0.0 32.928 4.0 33.024 ;
+        RECT 0.0 33.12 4.0 33.216 ;
     END 
   END O2[21]
   PIN O2[22]
     DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT 
       LAYER M4 ;
-        RECT 0.0 33.12 4.0 33.216 ;
+        RECT 0.0 33.312 4.0 33.408 ;
     END 
   END O2[22]
   PIN O2[23]
     DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT 
       LAYER M4 ;
-        RECT 0.0 33.312 4.0 33.408 ;
+        RECT 0.0 33.504 4.0 33.6 ;
     END 
   END O2[23]
   PIN O2[24]
     DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT 
       LAYER M4 ;
-        RECT 0.0 33.504 4.0 33.6 ;
+        RECT 0.0 33.696 4.0 33.792 ;
     END 
   END O2[24]
   PIN O2[25]
     DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT 
       LAYER M4 ;
-        RECT 0.0 33.696 4.0 33.792 ;
+        RECT 0.0 33.888 4.0 33.984 ;
     END 
   END O2[25]
   PIN O2[26]
     DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT 
       LAYER M4 ;
-        RECT 0.0 33.888 4.0 33.984 ;
+        RECT 0.0 34.08 4.0 34.176 ;
     END 
   END O2[26]
   PIN O2[27]
     DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT 
       LAYER M4 ;
-        RECT 0.0 34.08 4.0 34.176 ;
+        RECT 0.0 34.656 4.0 34.752 ;
     END 
   END O2[27]
   PIN O2[28]
     DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT 
       LAYER M4 ;
-        RECT 0.0 34.656 4.0 34.752 ;
+        RECT 0.0 34.848 4.0 34.944 ;
     END 
   END O2[28]
   PIN O2[29]
     DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT 
       LAYER M4 ;
-        RECT 0.0 34.848 4.0 34.944 ;
+        RECT 0.0 35.04 4.0 35.136 ;
     END 
   END O2[29]
   PIN O2[30]
     DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT 
       LAYER M4 ;
-        RECT 0.0 35.04 4.0 35.136 ;
+        RECT 0.0 35.232 4.0 35.328 ;
     END 
   END O2[30]
   PIN O2[31]
     DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT 
       LAYER M4 ;
-        RECT 0.0 35.232 4.0 35.328 ;
+        RECT 0.0 35.424 4.0 35.52 ;
     END 
   END O2[31]
   PIN O2[32]
     DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT 
       LAYER M4 ;
-        RECT 0.0 35.424 4.0 35.52 ;
+        RECT 0.0 35.616 4.0 35.712 ;
     END 
   END O2[32]
   OBS