drivers: ptp clock: ptp_clock_nxp_enet: extended pulse width of 1 PPS signal #97354
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… pulse Extended the pulse width of the 1 PPS output from 1 clock cycle to the maximum length (32 clock cycles). Signed-off-by: Frank Duerr <[email protected]>
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hakehuang
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| * pulse width of many devices, which are often in the range of milliseconds. | ||
| * However, 32 clock cycles is the upper limit. | ||
| */ | ||
| ENET_Ptp1588SetChannelOutputPulseWidth(data->base, kENET_PtpTimerChannel3, false, |
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this function depends on
#if defined(FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL) && FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL
and not all enet controller supports this. I would suggest to add a dts attribute for this.
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The pulse width of the 1 PPS output signal on NXP boards (ENET driver) is only one cycle of the PTP clock. For instance, at 25 MHz clock rate, the pulse width is only 40 ns. Other devices typically have orders of mangitude longer pulses in the range of milliseconds (e.g., 100 ms for many GPS devices or even 500 ms for the Intel i210 NIC).
This PR extends the 1 PPS pulse to its maximum width of 32 clock cycles (1.28 us). This is still very short compared to other devices, but better than the 1 clock cycle (40 ns) default value.
The following figure shows the resulting 1 PPS pulse from an i.MX RT1062 width the PR applied: