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10 changes: 10 additions & 0 deletions drivers/ptp_clock/ptp_clock_nxp_enet.c
Original file line number Diff line number Diff line change
Expand Up @@ -179,6 +179,16 @@ void nxp_enet_ptp_clock_callback(const struct device *dev,

ENET_Ptp1588SetChannelMode(data->base, kENET_PtpTimerChannel3,
kENET_PtpChannelPulseHighonCompare, true);

/* Set 1PPS pulse width to 32 clock cycles of PTP clock.
* At 25 MHz clock frequency, this amounts to a pulse width of 1.28 us.
* Note that this is still orders of magnitude shorter than the 1PPS
* pulse width of many devices, which are often in the range of milliseconds.
* However, 32 clock cycles is the upper limit.
*/
ENET_Ptp1588SetChannelOutputPulseWidth(data->base, kENET_PtpTimerChannel3, false,
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@hakehuang hakehuang Oct 11, 2025

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this function depends on
#if defined(FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL) && FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL
and not all enet controller supports this. I would suggest to add a dts attribute for this.

31, true);

ENET_Ptp1588StartTimer(data->base, ptp_config.ptp1588ClockSrc_Hz);
ENET_EnableInterrupts(data->base, ENET_TS_INTERRUPT);
}
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