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Merge pull request #3606 from alainmarcel/alainmarcel-patch-1
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gate defname in non-elab model
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@alaindargelas
alaindargelas committed Apr 20, 2023
2 parents 5adf8a2 + 1dcac51 commit e932b42
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Showing 13 changed files with 979 additions and 561 deletions.
1 change: 0 additions & 1 deletion include/Surelog/DesignCompile/UhdmWriter.h
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Expand Up @@ -68,7 +68,6 @@ class UhdmWriter final {
static uint32_t getStrengthType(VObjectType type);

static std::string builtinGateName(VObjectType type);
static uint32_t getBuiltinType(VObjectType type);

private:
void writePorts(std::vector<Signal*>& orig_ports, UHDM::BaseClass* parent,
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2 changes: 1 addition & 1 deletion src/DesignCompile/CompileHelper.cpp
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Expand Up @@ -2597,7 +2597,7 @@ void CompileHelper::compileGateInstantiation(ModuleDefinition* mod,
*/
if (gate) {
gate->VpiName(fC->SymName(Name));
// gate->VpiDefName(child->getModuleName());
gate->VpiDefName(UhdmWriter::builtinGateName(gatetype));
fC->populateCoreMembers(id, id, gate);
}
// writePrimTerms(child, gate, vpiGateType, s);
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61 changes: 1 addition & 60 deletions src/DesignCompile/UhdmWriter.cpp
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Expand Up @@ -149,65 +149,6 @@ std::string UhdmWriter::builtinGateName(VObjectType type) {
return modName;
}

uint32_t UhdmWriter::getBuiltinType(VObjectType type) {
switch (type) {
case VObjectType::slNInpGate_And:
return vpiAndPrim;
case VObjectType::slNInpGate_Or:
return vpiOrPrim;
case VObjectType::slNInpGate_Nor:
return vpiNorPrim;
case VObjectType::slNInpGate_Nand:
return vpiNandPrim;
case VObjectType::slNInpGate_Xor:
return vpiXorPrim;
case VObjectType::slNInpGate_Xnor:
return vpiXnorPrim;
case VObjectType::slNOutGate_Buf:
return vpiBufPrim;
case VObjectType::slNOutGate_Not:
return vpiNotPrim;
case VObjectType::slPassEnSwitch_Tranif0:
return vpiTranif0Prim;
case VObjectType::slPassEnSwitch_Tranif1:
return vpiTranif1Prim;
case VObjectType::slPassEnSwitch_RTranif1:
return vpiRtranif1Prim;
case VObjectType::slPassEnSwitch_RTranif0:
return vpiRtranif0Prim;
case VObjectType::slPassSwitch_Tran:
return vpiTranPrim;
case VObjectType::slPassSwitch_RTran:
return vpiRtranPrim;
case VObjectType::slCmosSwitchType_Cmos:
return vpiCmosPrim;
case VObjectType::slCmosSwitchType_RCmos:
return vpiRcmosPrim;
case VObjectType::slEnableGateType_Bufif0:
return vpiBufif0Prim;
case VObjectType::slEnableGateType_Bufif1:
return vpiBufif1Prim;
case VObjectType::slEnableGateType_Notif0:
return vpiNotif0Prim;
case VObjectType::slEnableGateType_Notif1:
return vpiNotif1Prim;
case VObjectType::slMosSwitchType_NMos:
return vpiNmosPrim;
case VObjectType::slMosSwitchType_PMos:
return vpiPmosPrim;
case VObjectType::slMosSwitchType_RNMos:
return vpiRnmosPrim;
case VObjectType::slMosSwitchType_RPMos:
return vpiRpmosPrim;
case VObjectType::slPullup:
return vpiPullupPrim;
case VObjectType::slPulldown:
return vpiPulldownPrim;
default:
return 0;
}
}

UhdmWriter::UhdmWriter(CompileDesign* compiler, Design* design)
: m_compileDesign(compiler), m_design(design) {
m_helper.seterrorReporting(
Expand Down Expand Up @@ -3685,7 +3626,7 @@ void UhdmWriter::writeInstance(ModuleDefinition* mod, ModuleInstance* instance,
const FileContent* fC = child->getFileContent();
NodeId gatenode = fC->Child(fC->Parent(child->getNodeId()));
VObjectType gatetype = fC->Type(gatenode);
int32_t vpiGateType = getBuiltinType(gatetype);
int32_t vpiGateType = m_helper.getBuiltinType(gatetype);
if (insttype == VObjectType::slUdp_instantiation) {
UHDM::udp* udp = s.MakeUdp();
gate = udp;
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12 changes: 8 additions & 4 deletions tests/CarryTrans/CarryTrans.log
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Expand Up @@ -1486,30 +1486,34 @@ design: (work@carry_rtl)
|vpiTypedef:
\_logic_typespec: , line:9:12, endln:9:12
|vpiPrimitive:
\_gate: (work@carry_gate.g1), line:12:5, endln:12:16
\_gate: work@and (work@carry_gate.g1), line:12:5, endln:12:16
|vpiParent:
\_module_inst: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10
|vpiDefName:work@and
|vpiName:g1
|vpiFullName:work@carry_gate.g1
|vpiPrimType:1
|vpiPrimitive:
\_gate: (work@carry_gate.g2), line:13:5, endln:13:16
\_gate: work@and (work@carry_gate.g2), line:13:5, endln:13:16
|vpiParent:
\_module_inst: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10
|vpiDefName:work@and
|vpiName:g2
|vpiFullName:work@carry_gate.g2
|vpiPrimType:1
|vpiPrimitive:
\_gate: (work@carry_gate.g3), line:14:5, endln:14:16
\_gate: work@and (work@carry_gate.g3), line:14:5, endln:14:16
|vpiParent:
\_module_inst: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10
|vpiDefName:work@and
|vpiName:g3
|vpiFullName:work@carry_gate.g3
|vpiPrimType:1
|vpiPrimitive:
\_gate: (work@carry_gate.g4), line:15:4, endln:15:21
\_gate: work@or (work@carry_gate.g4), line:15:4, endln:15:21
|vpiParent:
\_module_inst: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10
|vpiDefName:work@or
|vpiName:g4
|vpiFullName:work@carry_gate.g4
|vpiPrimType:4
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44 changes: 27 additions & 17 deletions tests/GateLevel/GateLevel.log
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Expand Up @@ -1537,65 +1537,75 @@ design: (work@LogicGates)
|vpiActual:
\_logic_net: ([email protected]), line:1:53, endln:1:56
|vpiPrimitive:
\_gate: (work@LogicGates), line:5:6, endln:5:14
\_gate: work@and (work@LogicGates.work@and), line:5:6, endln:5:14
|vpiParent:
\_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10
|vpiFullName:work@LogicGates
|vpiDefName:work@and
|vpiFullName:[email protected]@and
|vpiPrimType:1
|vpiPrimitive:
\_gate: (work@LogicGates), line:6:5, endln:6:13
\_gate: work@or (work@LogicGates.work@or), line:6:5, endln:6:13
|vpiParent:
\_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10
|vpiFullName:work@LogicGates
|vpiDefName:work@or
|vpiFullName:[email protected]@or
|vpiPrimType:4
|vpiPrimitive:
\_gate: (work@LogicGates), line:7:6, endln:7:12
\_gate: work@not (work@LogicGates.work@not), line:7:6, endln:7:12
|vpiParent:
\_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10
|vpiFullName:work@LogicGates
|vpiDefName:work@not
|vpiFullName:[email protected]@not
|vpiPrimType:8
|vpiPrimitive:
\_gate: (work@LogicGates), line:8:7, endln:8:15
\_gate: work@nand (work@LogicGates.work@nand), line:8:7, endln:8:15
|vpiParent:
\_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10
|vpiFullName:work@LogicGates
|vpiDefName:work@nand
|vpiFullName:[email protected]@nand
|vpiPrimType:2
|vpiPrimitive:
\_gate: (work@LogicGates), line:9:6, endln:9:14
\_gate: work@nor (work@LogicGates.work@nor), line:9:6, endln:9:14
|vpiParent:
\_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10
|vpiFullName:work@LogicGates
|vpiDefName:work@nor
|vpiFullName:[email protected]@nor
|vpiPrimType:3
|vpiPrimitive:
\_gate: (work@LogicGates), line:10:6, endln:10:14
\_gate: work@xor (work@LogicGates.work@xor), line:10:6, endln:10:14
|vpiParent:
\_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10
|vpiFullName:work@LogicGates
|vpiDefName:work@xor
|vpiFullName:[email protected]@xor
|vpiPrimType:5
|vpiPrimitive:
\_gate: (work@LogicGates), line:11:7, endln:11:15
\_gate: work@xnor (work@LogicGates.work@xnor), line:11:7, endln:11:15
|vpiParent:
\_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10
|vpiFullName:work@LogicGates
|vpiDefName:work@xnor
|vpiFullName:[email protected]@xnor
|vpiPrimType:6
|vpiPrimitive:
\_gate: ([email protected]), line:13:14, endln:13:25
\_gate: work@and ([email protected]), line:13:14, endln:13:25
|vpiParent:
\_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10
|vpiDefName:work@and
|vpiName:a1
|vpiFullName:[email protected]
|vpiPrimType:1
|vpiPrimitive:
\_gate: ([email protected]), line:14:13, endln:14:31
\_gate: work@or ([email protected]), line:14:13, endln:14:31
|vpiParent:
\_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10
|vpiDefName:work@or
|vpiName:a2
|vpiFullName:[email protected]
|vpiPrimType:4
|vpiPrimitive:
\_gate: ([email protected]), line:15:25, endln:15:38
\_gate: work@nand ([email protected]), line:15:25, endln:15:38
|vpiParent:
\_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10
|vpiDefName:work@nand
|vpiName:a3
|vpiFullName:[email protected]
|vpiPrimType:2
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