Skip to content

[Workflow] Fix VectorCGRA module gen pt. 1. #3

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
rp15 merged 10 commits into from
Dec 25, 2025
Merged

[Workflow] Fix VectorCGRA module gen pt. 1. #3

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
10 commits
Select commit Hold shift + click to select a range
b74fd41
[Workflow] Fix VectorCGRA module gen pt. 1.
rp15 Dec 24, 2025
fe765bb
[Workflow] Fix VectorCGRA module gen pt. 2.
rp15 Dec 24, 2025
df59c66
[Workflow] Fix VectorCGRA module gen pt. 3.
rp15 Dec 24, 2025
f181627
[Workflow] Fix VectorCGRA module gen pt. 4.
rp15 Dec 24, 2025
5e97162
[Workflow] Fix VectorCGRA module gen pt. 5.
rp15 Dec 24, 2025
458bafa
[Workflow] Fix VectorCGRA module gen pt. 6.
rp15 Dec 24, 2025
12ad598
[Workflow] Fix VectorCGRA module gen pt. 7.
rp15 Dec 24, 2025
a7d8b4b
[Workflow] Fix VectorCGRA module gen pt. 8.
rp15 Dec 24, 2025
17bf8eb
[Workflow] Fix VectorCGRA module gen pt. 9.
rp15 Dec 24, 2025
53ceff0
[Workflow] Test bench cleanup.
rp15 Dec 24, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
32 changes: 17 additions & 15 deletions .github/workflows/ci-acc-soc.yml
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -23,25 +23,24 @@ jobs:
with:
# same as `git submodule update --init` to update submodules
submodules: recursive
clean: true
- name: Set up Python ${{ matrix.python-version }}
uses: actions/setup-python@v3
with:
python-version: ${{ matrix.python-version }}

#- name: Install Verilator
# run: |
# wget https://github.com/tancheng/pymtl-verilator/raw/master/verilator-travis-4.036.tar.gz
# tar -C ${HOME} -xzf verilator-travis-4.036.tar.gz
# echo "VERILATOR_ROOT=${HOME}/verilator" >> $GITHUB_ENV
# echo "PYMTL_VERILATOR_INCLUDE_DIR=${HOME}/verilator/share/verilator/include" >> $GITHUB_ENV
# echo "${HOME}/verilator/bin" >> $GITHUB_PATH
- name: Install Verilator
run: |
wget https://github.com/tancheng/pymtl-verilator/raw/master/verilator-travis-4.036.tar.gz
tar -C ${HOME} -xzf verilator-travis-4.036.tar.gz
echo "VERILATOR_ROOT=${HOME}/verilator" >> $GITHUB_ENV
echo "PYMTL_VERILATOR_INCLUDE_DIR=${HOME}/verilator/share/verilator/include" >> $GITHUB_ENV
echo "${HOME}/verilator/bin" >> $GITHUB_PATH

#- name: Check Verilator
# run: |
# echo ${VERILATOR_ROOT}
# echo ${PYMTL_VERILATOR_INCLUDE_DIR}
# verilator --version
- name: Check Verilator
run: |
echo ${VERILATOR_ROOT}
echo ${PYMTL_VERILATOR_INCLUDE_DIR}
verilator --version

- name: Install dependencies
run: |
Expand Down Expand Up @@ -86,6 +85,9 @@ jobs:
run: |
mkdir -p build && cd build
source ${HOME}/venv/bin/activate
export PYTHONPATH=$PYTHONPATH:.
pytest ../VectorCGRA/multi_cgra/test/MeshMultiCgraRTL_test.py::test_multi_CGRA_fir_scalar_translation --collect-only --tb=short
pytest ../VectorCGRA/multi_cgra/test/MeshMultiCgraRTL_test.py --collect-only --tb=short
## Simulation across all tests.
#pytest .. -v --tb=short
## CtrlMemDynamicRTL
Expand Down Expand Up @@ -113,7 +115,7 @@ jobs:
## MeshMultiCgraTemplateRTL Test
#pytest ../multi_cgra/test/MeshMultiCgraTemplateRTL_test.py -xvs --test-verilog --dump-vtb --dump-vcd
# Generate .v file with explicit file & module names.
pytest ../multi_cgra/test/MeshMultiCgraRTL_test.py::test_multi_CGRA_fir_scalar_translation -xvs --test-verilog --dump-vtb --dump-vcd
pytest ../VectorCGRA/multi_cgra/test/MeshMultiCgraRTL_test.py::test_multi_CGRA_fir_scalar_translation -xvs --test-verilog --dump-vtb --dump-vcd

#- name: Test synthesis for CGRA template
# run: |
Expand Down Expand Up @@ -148,6 +150,6 @@ jobs:
unset PYMTL_VERILATOR_INCLUDE_DIR
mkdir -p build && cd build
verilator --version
verilator --binary -j 0 -Wno-UNOPTFLAT -Wno-WIDTHEXPAND -Wno-TIMESCALEMOD --error-limit 1000 --trace --timing -I../common_cells/include -I../axi/include -I../erv_RISC-V --top acc_soc_tb ../erv_RISC-V/ALUCtrl.v ../erv_RISC-V/dff.v ../erv_RISC-V/immGen.v ../erv_RISC-V/mainCtrl.v ../erv_RISC-V/risc5ALU_core.v ../erv_RISC-V/riscV.v ../common_cells/src/stream_mux.sv ../common_cells/src/stream_fork.sv ../common_cells/src/stream_fifo.sv ../common_cells/src/stream_join.sv ../common_cells/src/stream_fork_dynamic.sv ../common_cells/src/fifo_v3.sv ../common_cells/src/stream_join_dynamic.sv ../axi/src/axi_pkg.sv ../axi/src/axi_intf.sv ../axi/src/axi_to_detailed_mem.sv ../axi/src/axi_to_mem.sv ./MeshMultiCgraRTL__explicit__pickled.v ../src/imem_rom.sv ../src/dp_sram_axi_cpu.sv ../src/cgra_axis_bridge.sv ../src/axis_dma_duplex.sv ../src/acc_soc.sv ../verif/acc_soc_tb.sv
verilator --binary -j 0 -Wno-UNOPTFLAT -Wno-WIDTHEXPAND -Wno-TIMESCALEMOD -Wno-WIDTHTRUNC --error-limit 1000 --trace --timing -I../common_cells/include -I../axi/include -I../erv_RISC-V --top acc_soc_tb ../erv_RISC-V/ALUCtrl.v ../erv_RISC-V/dff.v ../erv_RISC-V/immGen.v ../erv_RISC-V/mainCtrl.v ../erv_RISC-V/risc5ALU_core.v ../erv_RISC-V/riscV.v ../common_cells/src/stream_mux.sv ../common_cells/src/stream_fork.sv ../common_cells/src/stream_fifo.sv ../common_cells/src/stream_join.sv ../common_cells/src/stream_fork_dynamic.sv ../common_cells/src/fifo_v3.sv ../common_cells/src/stream_join_dynamic.sv ../axi/src/axi_pkg.sv ../axi/src/axi_intf.sv ../axi/src/axi_to_detailed_mem.sv ../axi/src/axi_to_mem.sv ./MeshMultiCgraRTL__explicit__pickled.v ../src/imem_rom.sv ../src/dp_sram_axi_cpu.sv ../src/cgra_axis_bridge.sv ../src/axis_dma_duplex.sv ../src/acc_soc.sv ../verif/acc_soc_tb.sv
./obj_dir/Vacc_soc_tb

61 changes: 13 additions & 48 deletions verif/acc_soc_tb.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@ vcs -sverilog -full64 -timescale=1ns/1ps erv_RISC-V/ALUCtrl.v erv_RISC-V/dff.v e
common_cells/src/stream_mux.sv common_cells/src/stream_fork.sv common_cells/src/stream_fifo.sv \
common_cells/src/stream_join.sv common_cells/src/stream_fork_dynamic.sv common_cells/src/fifo_v3.sv common_cells/src/stream_join_dynamic.sv \
axi/src/axi_pkg.sv axi/src/axi_intf.sv axi/src/axi_to_detailed_mem.sv axi/src/axi_to_mem.sv \
VectorCGRA/multi_cgra/test/MeshMultiCgraRTL__explicit__pickled.v \
./MeshMultiCgraRTL__explicit__pickled.v \
src/imem_rom.sv src/dp_sram_axi_cpu.sv src/cgra_axis_bridge.sv src/axis_dma_duplex.sv src/acc_soc.sv verif/acc_soc_tb.sv \
-debug_access+all +incdir+common_cells/include +incdir+axi/include +incdir+erv_RISC-V -top acc_soc_tb
*/
Expand All @@ -16,6 +16,8 @@ module acc_soc_tb
logic [0:0] clk;
logic [0:0] reset;

int PASS = 'd0;

acc_soc dut ( .clk, .rstn(~reset) );


Expand Down Expand Up @@ -154,6 +156,9 @@ module acc_soc_tb
*/
repeat (2500) @(posedge clk);

if ('d1 == PASS) $display("\nTEST PASSED.\n");
else $display("\nTEST FAILED.\n");

// Inspect the first few destination packets.
for (int i=0;i<3;i++) begin
$display("DST packet %0d: %02x %02x %02x", i,
Expand Down Expand Up @@ -255,53 +260,13 @@ module acc_soc_tb
always @ (posedge clk or negedge clk)
begin
#1
$display("%d", dut.u_cpu.PC);
$display("%09b %04b", {dut.reg_irq_en, 6'b0, dut.reg_start_tx, dut.reg_start_rx}, {dut.stat_done_tx, dut.stat_busy_tx, dut.stat_done_rx, dut.stat_busy_rx});
/*$display("%t: clk %d reset %d recv_from_noc__rdy %d", $time(), clk, reset, recv_from_noc__rdy);
$display("%t: e_recv_rdy[0] %d e_in_val[0] %d e_recv_rdy[1] %d e_in_val[1] %d", $time(), recv_data_on_boundary_east__rdy[0], recv_data_on_boundary_east__val[0], recv_data_on_boundary_east__rdy[1], recv_data_on_boundary_east__val[1]);
$display("%t: recv_from_cpu_ctrl_pkt__rdy %d recv_from_cpu_ctrl_pkt__val %d val_rtl %d", $time(), recv_from_cpu_ctrl_pkt__rdy, recv_from_cpu_ctrl_pkt__val, CGRA.controller.recv_from_cpu_ctrl_pkt__val);
$display("%t: send_to_noc__val %d\n", $time(), send_to_noc__val);
$display("%t: CGRA.tile__0.const_mem.reg_file.regs[0] %d CGRA.tile__0.const_mem.reg_file.regs[1] %d CGRA.tile__0.ctrl_mem.reg_file.regs[0] %d CGRA.tile__0.ctrl_mem.reg_file.regs[1] %d", $time(), CGRA.tile__0.const_mem.reg_file.regs[0], CGRA.tile__0.const_mem.reg_file.regs[1], CGRA.tile__0.ctrl_mem.reg_file.regs[0], CGRA.tile__0.ctrl_mem.reg_file.regs[1]);
*/
//$display("%t: %d %d %d %d", $time(), CGRA.controller.recv_ctrl_pkt_queue.recv__val, CGRA.controller.recv_ctrl_pkt_queue.recv__msg, CGRA.controller.recv_ctrl_pkt_queue.send__val, CGRA.controller.recv_ctrl_pkt_queue.send__msg);
//$display("%t: %d %d %d %d", $time(), CGRA.ctrl_ring.recv__val[0], CGRA.ctrl_ring.recv__msg[0], CGRA.ctrl_ring.send__val[0], CGRA.ctrl_ring.send__msg[0]);
//$display("%t: tile00 cnst val %d tile00 cnst rdy %d msg %d", $time, MultiCGRA.cgra__0.tile__0.const_mem.recv_const__val, MultiCGRA.cgra__0.tile__0.const_mem.recv_const__rdy, MultiCGRA.cgra__0.tile__0.const_mem.recv_const__msg);
//$display("%t: recv_from_cpu_pkt__rdy %d recv_from_cpu_pkt__val %d", $time(), recv_from_cpu_pkt__rdy, recv_from_cpu_pkt__val);
//$display("%t: %d %d", $time, CGRA.tile__0.const_mem.__tmpvar__load_const_not_full, CGRA.tile__0.const_mem.wr_cur);
//$display("%t: %d %d %d", $time, CGRA.tile__1.const_mem.recv_const__val, CGRA.tile__1.const_mem.recv_const__rdy, CGRA.tile__1.const_mem.recv_const__msg);
//$display("%t: %d %d %d", $time, CGRA.tile__2.const_mem.recv_const__val, CGRA.tile__2.const_mem.recv_const__rdy, CGRA.tile__2.const_mem.recv_const__msg);
//$display("%t: %d %d %d", $time, CGRA.tile__3.const_mem.recv_const__val, CGRA.tile__3.const_mem.recv_const__rdy, CGRA.tile__3.const_mem.recv_const__msg);
/*$display("%t: cgra0datamem noc rd ready %d val %d", $time, MultiCGRA.cgra__0.data_mem.recv_from_noc_rdata__rdy, MultiCGRA.cgra__0.data_mem.recv_from_noc_rdata__val);
$display("%t: cgra0datamem waddr0 ready %d val %d", $time, MultiCGRA.cgra__0.data_mem.recv_waddr__rdy[0], MultiCGRA.cgra__0.data_mem.recv_waddr__val[0]);
$display("%t: cgra0datamem wdata0 ready %d val %d", $time, MultiCGRA.cgra__0.data_mem.recv_wdata__rdy[0], MultiCGRA.cgra__0.data_mem.recv_wdata__val[0]);
$display("%t: cgra0datamem waddr1 ready %d val %d", $time, MultiCGRA.cgra__0.data_mem.recv_waddr__rdy[1], MultiCGRA.cgra__0.data_mem.recv_waddr__val[1]);
$display("%t: cgra0datamem wdata1 ready %d val %d", $time, MultiCGRA.cgra__0.data_mem.recv_wdata__rdy[1], MultiCGRA.cgra__0.data_mem.recv_wdata__val[1]);
$display("%t: cgra0datamem waddr2 ready %d val %d", $time, MultiCGRA.cgra__0.data_mem.recv_waddr__rdy[2], MultiCGRA.cgra__0.data_mem.recv_waddr__val[2]);
$display("%t: cgra0datamem wdata2 ready %d val %d", $time, MultiCGRA.cgra__0.data_mem.recv_wdata__rdy[2], MultiCGRA.cgra__0.data_mem.recv_wdata__val[2]);
$display("%t: cgra0datamem waddr3 ready %d val %d", $time, MultiCGRA.cgra__0.data_mem.recv_waddr__rdy[3], MultiCGRA.cgra__0.data_mem.recv_waddr__val[3]);
$display("%t: cgra0datamem wdata3 ready %d val %d", $time, MultiCGRA.cgra__0.data_mem.recv_wdata__rdy[3], MultiCGRA.cgra__0.data_mem.recv_wdata__val[3]);
*/
//$display("%t: init_mem_done %d", $time, MultiCGRA.cgra__0.data_mem.init_mem_done);
// TODO $display("%t: ", $time);
/*$display("%t: cgra0datamem wdata0 ready %d val %d", $time, MultiCGRA.cgra__0.data_mem.recv_wdata__rdy[0], MultiCGRA.cgra__0.data_mem.recv_wdata__val[0]);
//$display("%t: cgra0rf0 wen %d", $time, MultiCGRA.cgra__0.data_mem.reg_file__wen[0][0]);
//$display("%t: cgra0rf1 wen %d", $time, MultiCGRA.cgra__0.data_mem.reg_file__wen[1][0]);
$display("%t: c0t1 ctrl mem 101 reg %d c0t1 ctrl mem 102 reg %d", $time, MultiCGRA.cgra__0.tile__1.ctrl_mem.ctrl_count_per_iter_val, MultiCGRA.cgra__0.tile__1.ctrl_mem.total_ctrl_steps_val);
//$display("%t: 102 val %d c_ac %d addr %d msg %d", $time,
//MultiCGRA.cgra__0.tile__1.ctrl_mem.recv_pkt_queue__send__val,
//MultiCGRA.cgra__0.tile__1.ctrl_mem.recv_pkt_queue__send__msg.ctrl_action,
//MultiCGRA.cgra__0.tile__1.ctrl_mem.recv_pkt_queue__send__msg.addr,
//MultiCGRA.cgra__0.tile__1.ctrl_mem.recv_pkt_queue__send__msg.data);
$display("!!!!!!!!!!!! %d", recv_from_cpu_pkt__msg.payload.ctrl.fu_in[1]);
$display("!!!!!!!!!!!! %d %d %d %d", send_to_cpu_pkt__val, send_to_cpu_pkt__msg.src, send_to_cpu_pkt__msg.dst, send_to_cpu_pkt__msg.payload.data.payload);
//$display("!!!!!!!!!!!. %d %d", MultiCGRA.cgra__0.tile__1.send_data__val[0], MultiCGRA.cgra__0.tile__1.send_data__msg[0].payload);
//$display("!!!!!!!!!!!. %d %d", MultiCGRA.cgra__0.tile__5.send_data__val[0], MultiCGRA.cgra__0.tile__5.send_data__msg[0].payload);
//$display("!!!!!!!!!!!. %d %d", MultiCGRA.cgra__0.tile__1.send_data__val[1], MultiCGRA.cgra__0.tile__1.send_data__msg[1].payload);
$display("!!!!!!!!!!!. %d %d %d", MultiCGRA.cgra__0.tile__5.send_data__val[1], MultiCGRA.cgra__0.tile__5.send_data__msg[1].payload, MultiCGRA.cgra__0.tile__5.send_data__msg[1].predicate);
//$display("!!!!!!!!!!!. %d %d", MultiCGRA.cgra__0.tile__1.send_data__val[2], MultiCGRA.cgra__0.tile__1.send_data__msg[2].payload);
//$display("!!!!!!!!!!!. %d %d", MultiCGRA.cgra__0.tile__5.send_data__val[2], MultiCGRA.cgra__0.tile__5.send_data__msg[2].payload);
//$display("!!!!!!!!!!!. %d %d", MultiCGRA.cgra__0.tile__1.send_data__val[3], MultiCGRA.cgra__0.tile__1.send_data__msg[3].payload);
//$display("!!!!!!!!!!!. %d %d", MultiCGRA.cgra__0.tile__5.send_data__val[3], MultiCGRA.cgra__0.tile__5.send_data__msg[3].payload);*/

if ( ( 'h100000 == dut.u_sram.mem[64'h0000_0000_0000_2000 >> 3]) &&
('h4f00238d10000000 == dut.u_sram.mem[64'h0000_0000_0000_2008 >> 3]) &&
( 'h1800001c000011 == dut.u_sram.mem[64'h0000_0000_0000_2010 >> 3]) )
begin
PASS = 1;
end
end

/*initial
Expand Down
Loading