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Verilog: add missing expression precedences #1390

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Nov 10, 2025
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Verilog: add missing expression precedences #1390

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2 changes: 2 additions & 0 deletions src/verilog/parser.y
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Original file line number Diff line number Diff line change
Expand Up @@ -581,6 +581,8 @@ int yyverilogerror(const char *error)
// following System Verilog 1800-2017 Table 11-2.
// Bison expects these in order of increasing precedence,
// whereas the table gives them in decreasing order.
%nonassoc '{'
%nonassoc '=' "+=" "-=" "*=" "/=" "%=" "&=" "^=" "|=" "<<=" ">>=" "<<<=" ">>>=" ":=" ":/"
%right "->" "<->"
%right "?" ":"
%left "||"
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