[ImportVerilog] Support use-before-declare across module bodies#10350
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[ImportVerilog] Support use-before-declare across module bodies#10350
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Predeclare module-scope variables, nets, interface instances, and module instances when slang is allowed to resolve names before their declarations. The predeclaration walk recurses through generated scopes, creates storage before expanding interfaces, and instantiates modules before earlier procedural code lowers, so forward references through local names, interface members, and hierarchical instance paths can resolve. Declaration initializers and net declaration assignments are lowered after the module body has populated the value map, then attached back to the original Moore declaration ops. This keeps the compatibility behavior behind --allow-use-before-declare and preserves existing diagnostics when the flag is absent. Add focused regression coverage for direct module declarations, generated scopes, interface instances, and module instances, plus broader expression/procedural compatibility matrices for common testbench patterns.
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@fabianschuiki Sorry about the prev PR state. Can this be reviewed ? |
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This is a frontend-only follow-up to the recent ImportVerilog virtual-interface work. It makes
--allow-use-before-declareusable across more module-body contexts without changing the default diagnostics when the option is absent.The importer now predeclares module-scope variables and nets through generated scopes, expands interface instances after storage predeclaration, and pre-instantiates module instances so earlier procedural code can resolve later hierarchical references. Declaration initializers and net declaration assignments are lowered after the module body has populated the value map, then attached back to the original Moore declaration ops.
The implementation stays behind
--allow-use-before-declareand does not add Arcilator/runtime behavior. The tests cover direct module declarations, generated scopes, interface instances, module instances, and broader expression/procedural compatibility matrices for common testbench-style patterns.Testing:
cmake --build build --target circt-verilog -- -j2cmake --build build --target circt-translate -- -j2build/bin/llvm-lit -sv test/Conversion/ImportVerilog