[ImportVerilog] Support use-before-declare across module bodies#10350

AmurG wants to merge 1 commit intollvm:mainllvm/circt:mainfrom

AmurG:amurg/uvm-pr3-importverilog-testbench-compatAmurG/circt:amurg/uvm-pr3-importverilog-testbench-compatCopy head branch name to clipboard