v3.0

What's Changed

This release has been a long time coming, bringing in a bunch of improvements and fixes. Here's a quick rundown:

• RTL Updates: Made it easier to configure the SoC and added support for the RISCV "C" extension and new SoC peripherals.
• AtomSim and Libcatom: feature additions, bug fixes, and improvements.
• Build Flow: Revamped the build process, introducing a new JSON-config-based flow.
• Documentation: major update!
• Docker Support: Now you can use Docker for development with our new Dockerfile.
• Updated CI workflows.

...and many more!

What's Changed

• Change Memory Map for HydrogenSoC, Add Arbiter by @saursin in #44
• fix config by @saursin in #46
• Dev by @saursin in #47
• Move SoC files to the SoC subdirectory by @saursin in #48
• Merge Dev into Main by @saursin in #49
• Docs update; Libc improvements by @saursin in #51

Full Changelog: v2.2...v3.0

v2.1

What's Changed

• Add DPI Logger by @saursin in #37

Full Changelog: v2.0...v2.1

v2.0

What's Changed

• Hydrogen soc by @saursin in #20
• Fpga Implementation of HydrogenSoC on Spartan6 Mini by @saursin in #22
• Better libc for RISCV-Atom by @saursin in #23
• Vuart by @saursin in #24
• Even Better Libc by @saursin in #25
• Dev by @saursin in #26
• Gpio by @saursin in #27
• Dualport Imem Added by @saursin in #28
• Better Printf & new libraries by @saursin in #31
• Add Software Implemented SPI by @saursin in #32
• Added basic CSR unit with cycle register by @saursin in #33
• Fix Atombones build by @saursin in #35
• Refactor RTL by @saursin in #36

Full Changelog: v1.2...v2.0

RISCV-Atom v1.2

• Bugfixes
• Corrected memory access protocol.
• All riscv-arch-tests passing.
• improved modularity.
• Cosmetic changes.

Better UI

• Lots of code refactoring.
• Better AtomSim & SCAR UI.
• Bugfixes.

AtomBones

• AtomBones completed and working
• Added RISC-V compliance tests for AtomBones
• SCAR implemented.