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Implemented a 2-cycle_calculator. Reference slide no - 36
Implemented a 2-cycle calculator with validity. Reference slide no - 41
Reference Slide No - 35 : Counter and Calculator with pipeline Rectified the previously implemented Counter and Calculator with pipeline as per the Reference Solution Diagram
Reference Slide no 36 Rectified the previously implemented 2 cycle calculator on Slide no 36 and verified it according to the reference solution output.
Reference Slide no 41 Rectified the previously implemented 2-cycle calculator with validity on Slide No 41, as per the reference solution diagram.
Reference Slide no - 43 Implemented Calculator_with_single_value_memory
Implemented Next PC
Implemented Fetch Logic
Implemented Next PC (Program Counter)
Implemented Fetch Logic
Implemented Instruction Types Decode
Implemented Instruction Immediate Decode
Implemented Instruction Decode
Implemented Instruction Field Decode
Implemented Instruction Decode Logic
Implemented Register File Read Part 1
Implemented Register File Read Part 2 - Slide 17
Implemented the Arithmetic and Logic Unit (ALU) - Slide No 18
Implemented Register File Write - Slide No 20
Implemented Branch Instructions 1 on Slide 21
Implemented Branch Instructions 2 on Slide No 22. Modified Program Counter(PC) to use the previous branch_target_pc when the previous instruction was from taken_branch.
Implemented the Testbench present on Slide No 25. The complete Day_4 assignment has been implemented and verified with the results.
Implementation of Pipelining logic starts.
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