Implemented a 2-cycle_calculator. Reference slide no - 36

Implemented a 2-cycle calculator with validity.  Reference slide no - 41

…myth-workshop-august-Redbeard358.git into master

Reference Slide No - 35 : Counter and Calculator with pipeline
Rectified the previously implemented Counter and Calculator with pipeline as per the Reference Solution Diagram

Reference Slide no 36
Rectified the previously implemented 2 cycle calculator on Slide no 36 and verified it according to the reference solution output.

Reference Slide no 41
Rectified the previously implemented 2-cycle calculator with validity on Slide No 41, as per the reference solution diagram.

Reference Slide no - 43
Implemented Calculator_with_single_value_memory

Implemented Next PC

Implemented Fetch Logic

Implemented Next PC (Program Counter)

Implemented Fetch Logic

Implemented Instruction Types Decode

Implemented Instruction Immediate Decode

Implemented Instruction Decode

Implemented Instruction Field Decode

Implemented Instruction Decode Logic

Implemented Register File Read Part 1

Implemented Register File Read Part 2 - Slide 17

Implemented the Arithmetic and Logic Unit (ALU) - Slide No 18

Implemented Register File Write - Slide No 20

Implemented Branch Instructions 1 on  Slide 21

Implemented Branch Instructions 2 on Slide No 22. Modified Program Counter(PC) to use the previous branch_target_pc when the previous instruction was from taken_branch.

Implemented the Testbench present on Slide No 25. The complete Day_4 assignment has been implemented and verified with the results.

Implementation of Pipelining logic starts.

Implemented 3 -Cycle RISC-V with pipelining.

Added partition logic into pipeline stages for 3-Cycle RISC-V - Slide No 37

Implementation of Register File Bypass Logic. Updated $src1_value and $src2_value to select previous $result.

Implemented branches in pipelining.

Implemented Complete Instruction Decode on Slide 44

Implemented Complete Arithametic and Logic Unit (ALU) by assigning values to all instructions - Slide No 45

Implemented Redirect Loads on Slide no 48

Rectified the syntax error at line no 232.

Implemented Load data to memory_1

Added the 1-R/W Memory and Implemented the Load data into memory_2.

Implemented the Load/Store program into the RISC-V using assembly language code. 
The final result value obtained after the summation result was stored to byte address 16, and was subsequently loaded from byte address 16 to register x17.

Implemented jump instructions and verified the output.
Thus, successfully completing the Implementation of  RISC-V Core.

Successfully completed implementing a RISC-V Core. This is the final code after clearing out all the clutters, arranging the code with indentations for better readability and comprehension.

Added the Makerchip Sandbox link for the project

Added the pipelining stage |calc and  @0

Getting acquainted with the pipelining technique in maker chip using TL-Verilog.

Removed the default reset signal and added reset into @0 pipeline stage

Initially tried the logic on my own, as per given on the slide.

Corrected the 2-Cycle Calculator after referring to the reference diagram. There is no need for reset_to_mux. And no need of any validity check in this slide, until now. So removed it. Also removed the default reset and added it to @0 stage.

Corrected the 2-cycle calculator code with validity code as per the reference diagram.  Changed $valid | $reset; to $valid | | $reset;  . $valid should be 1 bit.  No need of $valid || $reset in the $out expression.

Implemented the Calculator with Single Value Memory.

…myth-workshop-august-Redbeard358.git into master

…myth-workshop-august-Redbeard358.git into master

…myth-workshop-august-Redbeard358.git into master