Change generated kernel.xml axi manager port width to 512 #1074
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12 tasks
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Need to see where in hardware these changes need to be mirrored, not ready to be merged yet. |
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According to this, this PR should be fine as is and create the desired output, not causing any mismatches between |
rachitnigam
reviewed
Jul 6, 2022
src/backend/xilinx/xml.rs
Outdated
| @@ -150,7 +150,7 @@ impl Backend for XilinxXmlBackend { | |||
| name: axi_name, | |||
| mode: "master", | |||
| range: "0xFFFFFFFFFFFFFFFF", | |||
| data_width: 64, | |||
| data_width: 512, //matches actual hardware width | |||
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Can we leave a comment here explaining why this needs to be 512? Ideally pointing to documentation somewhere?
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Would this be good? Is there a deeper reason "why" that should be addressed?
Suggested change
| data_width: 512, //matches actual hardware width | |
| // Width should match the bus data width of memory modules | |
| // described in hardware, for example see | |
| // https://github.com/cucapra/calyx/blob/c2b12a0fe6b1ee3aaaae0c66e7c4619ee6c82614/src/backend/xilinx/toplevel.rs#L58 | |
| data_width: 512, |
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Once you add the comment explaining why it needs to be 512, merge it at your discretion! |
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Seems great! Maybe someday this magic 512 number should be configurable or something (and not written down twice), but that's for another day… |
nathanielnrn
added a commit
that referenced
this pull request
Jul 7, 2022
* Changed axi manager port width to 512 * Added comments regarding kernel width Co-authored-by: Nathaniel Navarro <[email protected]>
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