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Getting started with ispMACH 4256ZE Breakout Board

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rrwakc edited this page Jun 14, 2024 · 33 revisions

Getting started with ispMACH 4256ZE Breakout Board

The ispMACH 4256ZE Breakout Board is one of most simple (and thus very cheap) ispMach Evaluation Kit available from Lattice.

ispMACH 4256ZE Breakout Board

It offers you everything you need to start and explore complex programmable logic device (CPLD):

  • LC4256ZE-5TN144C CPLD with 96 I/O Pins
  • 8x red LED for trivial I/O Output
  • on-board FTDI FT2232HL for CPLD programming via JTAG protocol using USB 2.0 connection

DISCLAIMER

The guide bellow attempt to install required software in VirtualMachine (inside VirtualBox) to allow much easier maintenance and enhance possible project lifetime (unfortunately both hardware and software is aging very quickly - it is very hard to (say) after 10 years to be able to reprogram old CPLD - something like "digital trap").

Also, please note that license license.dat expires in 1-year

Thus all information here is provides without any warranty!

Kit Overview

Please download following to get basic information about this kit and demo source:

Please download both above files - there will be used later in this text so:

WARNING:

The above source project ispMACH4256ZEBreakoutBoardEvaluationKitSource.ZIP seems to differ a bit from what is described in PDF guide and already programmed on CPLD. The PDF references ispMACH4256ZE_BB_Eval_Kit_v01.0.zip, but I was unable to Google it - so it probably no longer exists :-)

Host computer setup

Your host (physical "bare metal") computer should at least have:

  • USB 2.0 port to connect this Kit (FTDI chip seems to no longer support USB 1.1)
  • CPU with Hardware virtualization support (tested old AMD X2)
  • 2GB RAM or more (tested 6GB)
  • OS: tested Windows 7, 64-bit

Please download and install following:

NOTE: Extension pack is required to support USB 2.0 pass-through (to make Kit visible inside guest VM). Plain VirtualBox supports USB 1.1 only, which does not work with recent FTDI chip.

Guest Virtual Machine (VM) setup

Unfortunately XP SP3 can't be used - I had no luck to start Synplify Synthesis under XP (it just exits without error message).

Therefore it is recommended to use Windows 7, 64-bit as Guest OS (so same as host OS n this example)

Basic setup:

  • Run Oracle VM VirtualBox Manager
  • click on New ... icon on toolbar
  • type name like win7-amd64-lattice - there should be already sensible defaults (Type: Microsoft Windows, Version: Windows 7 (64-bit)
  • following guest HW was used:
    • 1xCPU
    • 2GB RAM
    • 30GB dynamic disk (plenty of space)
    • you need to add/mount Windows 7,64-bit installation ISO (you need to get it yourself)
    • 2x network card (for easy access to VM):
      1. NAT (used to access Internet from XP VM)
      2. 'Host-only' (used to access guest VM from Host - unlike VMplayer the NAT (nor "NAT network") is not accessible from Host, unless "Port forwarding" (which is pain) is used).
    • also I prefer following in VM Settings...:
      • System -> Chipset: PIIX3
      • System -> Pointing Device: PS/2 Mouse (it is better than defualt USB Tablet)

Please install Window 7, 64-bit guest as usual. Also it is recommended to install VirtualBox Guest Additions (available in Guest VM menu).

Guest USB pass-through

There is needed special setup to be able to access Kit from guest VM.

You need to:

  • connect your Kit to USB 2.0
  • it should start immediately to run sample program:
    • green power LED should light on
    • red LEDs should flip-flop around 1s (in default demo there is intentional asymmetry in blinking interval)
  • your host OS (Windows 7) should have no drivers installed (this eases things much, because this avoids problem with HW reservation for VirtualBox)

Now run Oracle VM VirtualBox Manager

  • select you VM with Win Window 7,64-bit
  • click on Settings...
  • click on USB
  • check on Enable USB Controller
  • select radio button on USB 2.0 (EHCI) Controller
  • click on right on USB Connector with + icon
  • select (probably the only option) - Lattice FTUSB Interface Cable [0700]
  • click on OK to confirm passthrough

Start your guest:

  • when you right-click on bottom toolbar - icon of USB connector, you should see that our Lattice board is disconnect (it is OK for now)
  • guest VM should install USB root/hub drivers automatically

Install Lattice software

You need at least following software to successfully explore/program you Kit:

  • ispVM System 17.9 for Windows. This software accept JEDEC file (*.jed) on input and programs you CPLD device
  • ispLEVER Classic 2.0 Base Module. This program allows you to use Higher level abstraction for CPLD programming and generate JEDEC file needed for ispVM

IMPORTANT Notes:

  • It seems that exactly ispVM version 17.9 works in VirtualBox. I had no luck with other versions (for example version 18)
  • Please avoid ispLEVER Classic 1.4 or older. There is following problem:
    • demo project ispMACH4256ZEBreakoutBoardEvaluationKitSource.ZIP requires Synplify Pro plugin to be successfully opened. However it is not included in ispLEVER Classic <= 1.5 and it is available only via Form Request (not direct download provided).
    • thus you save lot of hassle using ispLEVERL Classic 1.6 or later (tested version 2.0)

Here are links for required Lattice software - install them inside your guest VM (Windows 7, 64-bit):

ispVM installation

ispVM is used to program our CPLD device from JEDEC (*.jed file) - it is a bit tricky to run it under VirtualBox successfully.

ispVM installation notes (do this inside guest VM):

  • please remember only version 17.9 seems to work under VirtualBox (verified under XP SP3,32-bit and Windows 7,64-bit guests)
  • run downloaded ispVMSystemV17.9.exe
  • install .NET framework 4.8 NETdp48-x86-x64-allos-enu.exe
  • please follow instructions from ispMACH4256ZEBreakoutBoardEvaluationKitUsersGuide.PDF (downloaded in "Kit Overview" section), chapter "Run the Demonstration Design"
  • when driver install dialog appears:
    • select FTDI 64-bit USB driver
    • click on Install button
    • when dialog requesting USB connect appears do:
      • disconnect your Kit from USB
      • after few seconds connect it again to USB
      • it should be attached to guest VM automatically (you may verify it - right-click on USB Connector Icon of bottom toolbar, you should see Lattice FTUSB Interface Cable [0700] prefixed with "Checked" sign)
      • wait until all required driver are installed (there should be rotating green ball on your Windows systray).
      • there should appear dialog that drivers were successfully installed
      • now you can click on Close button of driver dialog.
  • in the Windows strup folder create a date.bat file with line date 03/02/2019 or date matching the license, you can still update to at least Diomond 3.9 after this. This script will reset the date everytime you run the VM
  • this finished installation of ispVM

Please remember:

After each guest VM restart you need to disconnect and after few second connect your Kit to automatically attach your USB device to guest VM.

Testing programming of CPLD:

  • please extract demo source ispMACH4256ZEBreakoutBoardEvaluationKitSource.ZIP into suitable directory (I used c:\projects).
  • run ispVM from Start menu
  • setup USB connection using guide ispMACH4256ZEBreakoutBoardEvaluationKitUsersGuide.PDF, chapter Programming with ispVM
    • when you are asked to specify JEDEC (*.jed) file please use c:\projects\LC4256ZE_CTL\lc4256ze.jed
  • if the last step from PDF guide Project -> Download succeeds - your are ready to continue further

ispLEVER Classic installation

ispLEVER 2.0 and its plugins are used to Design function of our CPLD using higher level abstractions (the JEDEC file is very low level - basically just content of configuration FLASH memory).

Again - all instructions are done in guest VM:

  • extract downloaded ispLEVER_Classic_Base_2_0.zip
  • run extracted installer - file ispLEVER_Classic_Base_2_0.exe
  • be sure to DESELECT "ispVM" component (we already installed version 17.9 - the only that is known to work under VirtualBox).
  • after a while installer should finish succesfully

After install you need to:

  • restart OS - otherwise you can get error window registry is set improperly (see http://www.latticesemi.com/en/Support/AnswerDatabase/2/8/3/2832)
  • put license.dat (you should already receive it by e-mail from Lattice) somewhere in your guest VM (I copied it to C:\projects directory)
  • run ispLEVER and specify your license.dat file - it should be accepted without problems.

WARNING! Some components - for example Aldec Active-HDL - require that license.dat must be copied exactly to location pointed by environment variable:

echo %LM_LICENSE_FILE%
C:\ispLEVER_Classic2_0\license\license.dat;

In my case I needed to copy license.dat into c:\ispLEVER_Classic2_0\license\license.dat too.

Rebuilding demo code

  • run ispLEVER Project Naviagtor
  • Open Project c:\projects\LC4256ZE_CTL\LC4256ZE.syn
  • select LC4256ZE-5TN144C in Navigator Window
  • in Process ... window right-click Fit Design
  • click on Force to regenerate all files
  • it should build without error (just warning)
  • after build you can try Project -> Download in your ispVM to reprogram Kit (should work)

Modifying source - showing 8-bit binary counter on LEDs

We will try to replace LED flip-flop with 8-bit binary counter output.

  • be sure you have running ispLEVER Project Navigator
  • Open Project c:\projects\LC4256ZE_CTL\LC4256ZE.syn
  • right-click on [count_osc (lc4256ze.v)]
  • click on Open of context menu
  • change source to
// 8-bit binary counter displayed directly on LEDs
module count_osc (led);

  output [7:0]  led;
  reg    [7:0]  c_delay;

  defparam I1.TIMER_DIV = "1048576";
  OSCTIMER I1 (.DYNOSCDIS(1'b0), .TIMERRES(1'b0), .OSCOUT(osc_clk), .TIMEROUT(tmr_clk));

  assign led[7:0] = ~ c_delay ;

  always @(posedge tmr_clk) 
    begin
        c_delay <= c_delay + 1 ;
    end

endmodule
  • click on Save (Ctrl-S or Floppy icon)
  • back in ispLEVER project navigator

Update JEDEC file using again:

  • select LC4256ZE-5TN144C in Navigator Window
  • in Process ... window right-click Fit Design
  • click on Force to regenerate all files
  • it should build without error (just warning)

After build you can reprogram device using commont setup:

  • after build you can try Project -> Download in your ispVM to reprogram Kit (should work)

Fixing LED output order

Above 8-bit LED counter has swapped output bits (LED numbers does not correspond to counter bits properly). We can fix it (thanks for really good tutorial from http://pen.phys.virginia.edu/daq/lattice/doc17819x60.pdf).

To fix PIN to LED assignment do:

  • open ispMACH4256ZEBreakoutBoardEvaluationKitUsersGuide.PDF and go to page 4 and look at "Figure 6. J1 Header Landing and LED Array Callout", there PIN to LED assignment:
LED    PIN
D8 ->  |58|59|60|61| <- D5
D4 ->  |62|63|70|71| <- D1

Now we can:

  • double click on c:\projects\LC4256ZE_CTL\LC4256ZE.syn to run ispLEVER Project Navigator
  • in left Window Sources in Project select the text LC4256ZE-5TN144C (right after yellow chip icon)
  • in right Window Processes for Current Source double-click on Constraint Editor (should be the 2nd row)
  • after a while Constraint Editor should appear
  • ensure that top-level count_osc is selected
  • now fix pin assignments accroding to table, at least

NOTE: To avoid PIN number collisions you must temporarily choice unused PINS!!! (ehm!)

Signal/Group Name  | Pin 
_led_0_            | 71
_led_1_            | 70
_led_2_            | 63
_led_3_            | 62
_led_4_            | 61
_led_5_            | 60
_led_6_            | 59
_led_7_            | 58
  • Please double check Signal <-> Pin mapping
  • click on Floppy or press Ctrl-S to Save new Pinout
  • close Constraint Editor

Ensure that text LC4256ZE-5TN144C after yellow chip is still selected

  • right-click on Fit Design in Processes ... Window
  • click on Start context-menu

There should be no error, just old known warning:

<Warning>  P38466:  DYNOSCDIS and TIMERRES have the same logic.

You can ignore them.

Reprogram Kit as usual using ispVM.

If you edited pins correctly than the LED blinking frequency should be fastest on D1 and slowest on D8

Start counter with 0

Currently the counter seems to start at random value on Power UP (or semi random). I never though that fixing such small thing would take me half a day (but welcome to Complex PLD world :-)

Thanks to tip from https://github.com/cliffordwolf/yosys/issues/103#issuecomment-159942573 modify your source this way [count_osc (lc4256ze.v)] (see new ready register):

// 8-bit binary counter displayed directly on LEDs
module count_osc (led);
  output [7:0]  led;
  reg    [7:0]  c_delay;

  reg ready = 0;

  defparam I1.TIMER_DIV = "1048576";
  OSCTIMER I1 (.DYNOSCDIS(1'b0), .TIMERRES(1'b0), .OSCOUT(osc_clk), .TIMEROUT(tmr_clk));

  assign led[7:0] = ~ c_delay ;

  always @(posedge tmr_clk) 
    begin
      if (ready)
        c_delay <= c_delay + 1 ;
      else
      begin
        c_delay <= 8'd0;
        ready = 1;
      end
    end

endmodule
  • Save, rebuild, reprogram
  • disconnect and connect your Kit - it should start from blank diodes (zero) to count up :-) Uff!

Copyright © Henryk Paluch. All rights reserved.

Creative Commons License This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License

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